Investigation of negative differential resistance on negative capacitance Germanium source vertical TFET

Abstract

In this article, a systematic investigation of negative differential resistance (NDR) on a negative capacitance Germanium source vertical TFET (NC-Ge-vTFET) is presented. The implementation and increased ferroelectric (FE) film thickness (t FE) offers a significantly high current ratio, improved subthreshold slope, high transconductance with a very low hysteresis voltage. However, NDR is exhibited and is increasingly prominent at lower gate voltage and higher t FE due to the coupling of the internal gate and drain voltages. NDR is an undesired effect in analog circuits that has to be mitigated. To suppress the impacts of NDR on the device, different approaches are carried out: varying the overlap channel thickness, gate length, drain doping and gate-drain underlap. Circuit analysis is carried out with the implementation of NC-Ge-vTFET as digital inverter. When the gate-drain underlap length is increased from 0 nm to 15 nm, the propagation delay is significantly reduced by 30.98%. Benchmarking of the proposed device has also been carried out. This renders the gate-drain underlapped NC-Ge-vTFET to be a viable candidate for high performance, nanoscale, low power digital applications.