Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap

Abstract

Design of TFETs, with gate-drain underlap (Lun), exhibit suppressed off-state leakage and ambipolar conduction, thereby achieving larger on-to-off current ratio. In this work, through TCAD simulation study, we proposed an optimum value for gate-drain underlap length (Lun), and highlighted the advantages of designing TFETs with gate-drain underlap. Simulation framework was developed for both homojunction and heterojunction TFETs. The device design for both types of TFETs, considered similar doping profiles. The optimum value for Lun was determined to be half the gate length (Lg) from the DC characteristics, with little dependence of off-state leakage on the drain voltage. In the simulation study we also focused on the effect of the drain doping, and the gate length (Lg) on the performance of drain underlapped TFETs. The simulation study has been extensively performed on Ultra-Thin Body (UTB) III-V homojunction TFET and Ultra-Thin Body-Silicon On insulator (UTBSOI) Staggered gap (SG) III-V heterojunction TFET.