Achieving Near‐Ideal Subthreshold Swing in P‐Type WSe2 Field‐Effect Transistors

Abstract

AbstractThe pursuit of near‐ideal subthreshold swing (SS) ≈ 60 mV dec−1 is a primary driving force to realize the power‐efficient field‐effect transistors (FETs). This challenge is particularly pronounced in 2D material‐based FETs, where the presence of a large interface trap density (Dit) imposes limitations on electrostatic control, consequently escalating power consumption. In this study, the gate controllability of 2D FETs is systematically analyzed by fabricating pre‐patterned van der Waals (vdW)‐contacted p‐FETs, varying the WSe2 channel thickness from monolayer to ten‐layer. As a result, the channel thickness is optimized to achieve efficient gate controllability while minimizing Dit. The findings demonstrate negligible hysteresis and excellent subthreshold swing (SSmin) close to the thermal limit (≈60 mV dec−1), with a corresponding Dit of ≈1010 cm−2 eV−1, comparable to Dit values observed in state‐of‐the‐art Si transistors, when utilizing WSe2 channel thicknesses ≥ five‐layer. However, reducing the WSe2 channel thickness below the trilayer, SSmin (≈91 mV dec−1) deviates from the thermal limit, attributed to a comparatively higher Dit (≈1011 cm−2 eV−1), despite the still lower than values reported for surface‐contacted 2D transistors. Furthermore, all devices exhibit consistent p‐type characteristics, featuring a high ION/IOFF ratio, high mobility, and excellent electrical stability confirmed over several months.