Simulation of the Germanium-Tin Tunneling Field-Effect Transistors with a Ge Cap Layer: Improved Subthreshold Swing and Ion/Ioff Ratio

Abstract

Tunneling field-effect transistors (TFETs) have been proposed as the possible candidates to replace the traditional MOSFETs for the ultrascaled low power applications [1]. The band-to-band tunneling (BTBT) of TFETs can achieve the sub-60 mV/dec subthreshold swing (SS). Recently, GeSn alloys are attracting interest for TFETs application due to the direct band gap and high carrier mobility [2]. The large interface trap density (Dit) at the GeSn/high-k interface degrades the GeSn device performance [3,4]. However, the effects of Dit have not been fully considered for the device structure design and optimization of GeSn TFETs at present. This work examines the Dit effects on GeSn TFETs performance by numerical simulation. The influences of a Ge cap layer on planar GeSn TFETs are investigated. Figure 1 illustrates the simulated GeSn pTFETs with and without the Ge cap layer. The Dit effects are included in the simulation, and the corresponding simulated structures are summarized in Table I. The dynamic nonlocal BTBT model in Synopsys Sentaurus device simulator is adopted to calculate both the direct and indirect tunneling currents of GeSn TFETs. We calculate the electron band structures of GeSn alloys by the nonlocal empirical pseudopotential method, and the carrier effective masses are extracted from the developed band diagrams. The Luttinger parameters [5] are extracted, and the hole density-of-states effective masses are calculated based on the spherically averaged light hole and heavy hole masses [6]. Some key parameters used in the simulation are listed in Table II. The effects of Dit on the Ge0.94Sn0.06 TFETs performance are evaluated (Fig. 2). The direct tunneling is the dominant component of the total tunneling current. The Dit has significant effects on both the direct and indirect tunneling. The Dit worsens the SS, and leads to the decreased driving current and the increased leakage level. To suppress the Dit effects, the Ge0.94Sn0.06 TFETs with 2-nm-thick and 5-nm-thick Ge cap layers are simulated (Fig. 3). For the 2 nm cap layer device, the better Dit would improve the SS and leakage current. In addition, the 2 nm Ge layer is effective to suppress the BTBT leakage current (inset of Fig. 3), which has a significant impact on decreasing the SS. Hence, the 2 nm Ge capped Ge0.94Sn0.06 TFETs achieve an enhanced driving current at the low supply voltages. The minimum point SS and Ion/Ioff ratio are extracted and compared in Fig. 4. The Voff is defined as the Vgs at the drain current of 50 pA/μm. The supply voltage Vdd is 0.4 V, and thus the Von and Ion are determined. The Ion/Ioff ratio is denoted as Ratio1. The minimum SS decreases from 56.3 mV/dec to 32.9 mV/dec when the 2 nm Ge layer is used, and the Ratio1 is also improved. For the 5 nm cap device, the leakage current is lower due to the best Dit and the further suppressed leakage, but the relative thick Ge layer will affect the tunneling current. Figure 5 presents the comparison of the on-state BTBT rate. The 2 nm Ge cap layer doesn’t have obvious effect on the BTBT rate compared with the no-capped device. However, for the 5 nm cap device, Ge BTBT contributes more to the total current, and the GeSn BTBT is weakened, leading to the degradation of SS and Ratio1. For larger Sn composition (8.5%), SS is degraded due to the Dit and leakage, but the enhanced BTBT may increase Ion (Fig. 4). Moreover, Voff is also extracted at the lowest leakage level, and the corresponding obtained Ion/Ioff ratio is denoted as Ratio2. The 2-nm-capped Ge0.94Sn0.06 device exhibits the best Ratio2 (Fig. 4), reflecting the benefit for low power applications. In summary, the SS and Ion/Ioff ratio of GeSn TFETs can be improved by inserting a Ge cap layer. The ultrathin cap layer will not affect the GeSn BTBT, and can suppress the leakage current. Although the large band gap material is commonly not preferred for BTBT, the Ge cap layer may be needed for GeSn TFETs from the practical point of view. The device performance can be further improved by structure optimization. Acknowledgments: This work was supported in part by the National Natural Science Foundation of China (No. 61306105). [1] C. Hu et al., IEDM, pp. 387, 2010. [2] Y. Yang et al., IEDM, pp. 379, 2012. [3] Y. Qiu et al., JAP 115, 234505, 2014. [4] S. Gupta et al., IEDM, pp. 375, 2012. [5] K. L. Low et al., JAP 112, 103715, 2012. [6] A. Baldereschi et al., PRB 8, 2697, 1973. Figure 1