Comparison of Current Mirrors Designed with TFET or FinFET Devices for Different Dimensions and Temperatures

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The continuous MOSFET device scaling turned short channel effects and leakage currents into major issues, in a way that new technologies should be considered for further technology nodes. In this context, Tunnel Field Effect transistors (TFETs) are a promising alternative, in which gate controlled band-to-band tunneling (BTBT) replaces drift-diffusion in providing carrier injection[1-2]. The built-in tunnel barrier makes it possible to reach subthreshold swing (SS) values lower than ln(10).k.T/q (60mV/dec at room temperature), reducing power dissipation and leakage currents[1-2]. However low on-state current and ambipolarity are relevant issues, some simple circuits can be used to infer how recent devices compare to traditional structures. In this work, TFET devices have been studied based on experiments and simulations of a basic current mirror. Their performance has been compared to FinFETs for temperatures ranging from 300K to 500K. Fig.1 represents schematically the basic current mirror, with a fixed bias in the input transistor and a varying drain voltage applied to the output device. All measurements and simulations have been performed with VS1=VS2=1.7V and with VDS2ranging from -0.5V to 1.0V. Input and output drain currents have been analyzed. First of all, this circuit has been experimentally studied, making use of TFETs (Fig.2) and FinFETs (Fig.3) with different values of channel length (1µm and 10µm) and width (1µm and 0.25µm). Since for TFET the input transistor is under a fixed bias, its drain current is basically constant. Meanwhile, the output drain current decreases when VD2gets closer to 1.0V, since it is not in the “saturation-like” region anymore. Comparing Figures 2 and 3, it is clear that TFETs and FinFETs, respectively, present the same susceptibility to the channel width variation. On the other hand, it is quite interesting to notice the difference in terms of channel length dependence. Comparing IDSwhen L gets 10 times larger, FinFETs present the expected 10 times decrease, while TFETs reveal a reduction of no more than 20%, since TFET is not as length dependent as FinFET. Based on these observations, simulations have been performed to reveal the channel length influence on the suitability of both TFETs and FinFETs for current mirror circuits. All the simulations have been performed for an input transistor with L1 = 60nm, while the output transistor had L2 ranging from 20nm to 100nm. Figure 4 shows the IDS2/IDS1 ratio for each case when VDS2=0V, with the perfect matching situation represented by L2=L1=60nm. The results show that TFET is much less dependent on L2 than FinFET. Therefore, it is interesting to notice that the circuit presents a very good mirror behavior even when the transistors channel lengths do not exactly match. This is a consequence of the previously mentioned TFET working principle, with the tunneling happening quite close to the source/channel junction. The drain current is affected by L2only when it gets lower than 40nm, which may be explained by the impact of DIBT (drain induced barrier thinning) on TFETs[3]. On the other hand, a circuit with FinFETs loses its ability to mirror the input current when L2 changes. For instance, when L2 changes from 40nm to 100nm, the output drain current variation reaches 50%, while it varies less than 10% for TFETs. In the worst-case scenario for both of them (L2=20nm), the output drain current deviation from the perfect matching situation reaches 80% for TFETs and 230% for FinFETs. Finally, Fig.5 illustrates the temperature impact on the current mirror output current, revealing 2 main differences between TFETs and FinFETs. The first one is the opposite trend, with an ascending curve only for the TFET case. This may be explained by the differences in the transport mechanisms for each case. In TFET devices, higher temperatures increase band-to-band tunneling, which is the most important component for high values of VDS. Meanwhile, the mobility in FinFETs is degraded, resulting in a drain current decrease to almost half of its original value. Besides, dashed lines in Fig.5 reveal the susceptibility to the output drain voltage. These curves show the obtained results for VD2=-0.5V and VD2=+0.5V. While for TFETs this variation causes an output current deviation of 6%, for FinFETs the deviation reaches almost 30%. In other words, circuits with TFETs tend to present a larger compliance voltage, which is exactly the maximum voltage variation that still results in an acceptable output current. Therefore, TFETs present a better suitability in terms of mirroring the input current even for output bias variations. [1] W.M.Reddick et al.,Appl.Phys.Lett.,67,494-496,(1995). [2] T.Krishnamohan et al.,Tech.Dig. IEDM 2008,947-950,(2008). [3] M.D.V.Martino et al.,SBMicro 2014,1,1-4,(2014). Figure 1