Cellulose-Derivative-Based Gate Dielectric for High-Performance Organic Complementary Inverters.

Abstract

An ultra-thin natural-source-based cellulose derivate is used in a bilayer gate dielectric for organic complementary inverters. Extraordinarily high small-signal gains up to 1600, a very sharp transition region (as low as 40 mV), a full rail-to-rail swing, a balanced noise margin of 92.5%, and “long-time” stability are shown, revealing that these inverters are highly suitable for complex circuit designs. For more than a decade now the research in organic electronics was driven by unique consumer markets demanding for electronic circuits on flexible substrates over large areas and ideally at low cost. Meanwhile, versatile macroelectronic applications with attractive form factors such as flexible displays,1-4 large-area sensor arrays,5-11 e-paper,12, 13 low-cost radio-frequency identification tags,14-18 and bendable microprocessors19 have been realized using organic thin-film transistors (OTFTs) as the essential element. In the majority of these applications OTFTs are integrated either in the form of arrays or as digital logic. The fundamental building block of digital logic is the inverter, a circuit that inverts an input signal. Much work has been devoted in the last five years to design unipolar inverters using p-type-only OTFTs.18-23 Unfortunately, unipolar logic based on single gate OTFTs always suffers from high power consumption and low noise margin coupled with high noise margin variability and therefore impedes the fabrication of complex circuits having hundreds or more logic gates.19, 22, 23 In this context, it stands beyond doubt that the integration of both n-type and p-type transistors in complementary organic-based circuits12 is very advantageous due to a lower power dissipation, higher noise margin, better operational stability, and easier design of the circuit.24-27 To date, several major obstacles complicated the development of organic complementary circuits, which are as follows: i) the lack of n-channel OTFTs with a performance comparable to the p-channel OTFTs, ii) the challenge of device stability (difficulty in fabricating OTFTs with hysteresis-free characteristics), and iii) the difficulty in fabricating sufficiently thin gate dielectrics allowing for low supply voltages. Although many recently reported complementary organic inverters are impressive with respect to their low operation voltages (≤5 V),27-36 high static gains (>100 V/V),25, 28, 30, 32 and large noise margins (>80%),25, 35, 37, 38 only few of those can combine low-voltage operation with high gain and sufficient immunity against electrical noise.39 Moreover, there have been few investigations of the influence of hysteresis and threshold voltage shifts on the inverter characteristics, which typically gives rise to electrical instabilities and performance limitations of those devices.32, 39 The inverter's noise margin is the most critical parameter, since it directly determines the maximum complexity of circuits.22 Particularly, interesting applications of organic electronic circuits are found in analog electronics that allow for the read-out and processing of signals from printed large-area sensors and form an interface to silicon electronics. Examples are analog-to-digital (A/D) converters, operational amplifiers, and comparators, all including several tens of transistors, thus requiring both high gain and a large noise margin to be functional as well as sufficient processability. It is interesting to note that the majority of organic complementary inverters already mentioned24-34, 36-40 relied on pentacene as the p-type semiconductor (14 incidences), fluorinated copper phthalocyanine (6 incidences), or N,N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (5 incidences) as the n-type material. On the contrary, the variation in gate dielectric materials that are used is much higher with an emphasis on hybrid dielectric systems. Hybrid systems allow accounting for both a high dielectric breakdown voltage and an engineered interface to the semiconductor. Moreover, the implementation of biodegradable and biocompatible materials represents a new niche in the organic electronics research, aimed to address the issues of cost and toxicity to humans and environment posed by nowadays electronics, a topic that was recently reviewed elsewhere.41-43 Accordingly, we have demonstrated the usage of a novel hybrid and biodegradable high-k gate dielectric material system based on a cellulose derivative for low-voltage complementary organic circuits with exceptional high noise margins.35 Previous work done in our laboratories demonstrated the fabrication feasibility of complex circuits, where the electrode patterning was performed by a self-aligned photolithography technique.44, 45 This process can easily be transferred to an anodized aluminum (Al2O3) + trimethylsilyl cellulose (TMSC) based bilayer system; the respective results will be published soon. To follow on this preliminary work we have developed an extraordinarily well-performing complementary inverter technology based on a hybrid dielectric composed of a bilayer of alumina (Al2O3) and trimethylsilyl cellulose (TMSC) and pentacene or C60 for the p-channel and the n-channel organic semiconductor, respectively. It outperforms any inverter reported so far with respect to the combination of excellent key parameters, such as record DC gain of above 500 V/V, low operation voltage of only 4 V, and large noise margin up to 92.5%. In order to clarify the origin for this high performance, special attention is given to the investigation of the semiconductor–dielectric interface, the semiconductor morphology, the nature of traps, the influence of mobility levels on the inverter performance and its long-term stability. This article is not meant to report new materials and systems, but rather find explanations and present a thorough analysis of the extraordinary performance of the cellulose derivative (TMSC) dielectric and the TMSC to semiconductor interface in organic field-effect transistors and simple inverter circuits. All OTFTs presented in this work have a bottom gate, top contact device architecture, as illustrated in Figure 1a. The transistor fabrication process is described in detail in the Experimental Section. The semiconducting layer is pentacene for p-type and C60 (fullerene) for n-type conduction. For the gate dielectric, an inorganic (Al2O3)–organic (TMSC) bilayer is chosen with 28 and 30 nm layer thickness, respectively. The dielectric properties of both single-layer TMSC films and bilayer Al2O3 + TMSC films, were investigated by current–voltage (I(V)), capacitance–frequency (C(f)), and capacitance–voltage (C(V)) measurements in appropriate capacitor structures with 72 nm insulator layer thickness of pure TMSC and 28 + 30 nm of bilayer film of Al2O3 + TMSC, respectively. In Figure 1b, the I(V) curves of a representative capacitor formed by a single layer cellulose dielectric is shown, whereas in Figure S1a (in the Supporting Information) the curve with bilayer dielectric is displayed. A comparison of I(V) curves of a single layer and bilayer dielectric is displayed in Figure 1c. At an electric field of 3.0 MV cm−1 (equivalent to ≈22 V) a current density on the order of 10−6 A cm−2 is observed for the single-layer TMSC. A breakdown field of 4.5 ± 0.3 MV cm−1 is extracted from eight appropriate capacitor structures. One representative C(V) measurement is displayed in Figure 1d. Its capacitance of about 29 nF cm−2 corresponds to a dielectric constant of εR = 2.4 ± 0.2 at 1 kHz with an excellent stability at frequencies down to 0.5 mHz (virtually flat dielectric constant and low dielectric losses which are indicative of a high purity and negligible amount of mobile ionic species) as illustrated in Figure 1e.46 In comparison, capacitors based on the bilayer dielectric have three orders of magnitude lower leakage currents (≈10−9 A cm−2) at an electric field of 3.0 MV cm−1 corresponding to ≈17.5 V and an effective capacitance of 53 nF cm−2 at 1 kHz (see Figure S1a,b, Supporting Information). As can be derived from Figure S1c (in the Supporting Information) the permittivity of the bilayer dielectric also shows excellent stability over the tested frequency range (1 mHz to 10 kHz). The measured capacitance value of the dielectric is in good agreement with calculations by assuming a permittivity of 9 and a thickness of 28 nm for the Al2O3 layer as well as a measured permittivity of 2.4 ± 0.2 (Figure 1e) and 30 nm thickness for the TMSC layer (see the Experimental Section). In any OTFT with bottom gate architecture the surface properties of the gate dielectric (surface energy, surface roughness) decisively affect the arrangement and growth of small molecule semiconductors. The surface energy of spin-coated TMSC thin films was determined by contact angle measurements. With a water contact angle of 98.5°, TMSC can be regarded as a hydrophobic, low energy surface material with a total surface energy of γ = 24.2 ± 0.6 mN m−1, separable in a small polar component γP = 1.8 ± 0.5 mN m−1 and a dispersive component γD = 22.4 ± 0.1 mN m−1. The average surface roughness, indicated by the root mean square (rms)–roughness values, was found to be only 0.77 ± 0.1 nm by atomic force microscopy (AFM) measurements. On this smooth and low energy TMSC surface, a small-grain growth mode with average grain sizes between 150 and 300 nm for pentacene (shown in Figure 1a) and 50 nm for C60 was observed by AFM measurements. In Figure 2, typical electrical characteristics of OTFTs with either C60 or pentacene as the semiconducting layer are plotted. Both p- and n-type transistors are based on the inorganic–organic bilayer gate dielectric composed of Al2O3 and TMSC. The output characteristics ID(VDS) are displayed in Figure 2a,b, whereas the transfer characteristics ID(VGS) are shown in Figure 2c,d. Both transistor types display very small hysteresis between forward and reverse voltage sweeps. The output characteristics show clear saturation, but for the pentacene-based OTFT a non-linear behavior of the drain current at very low drain voltages is observable (Figure 2b). Such an S-shape of the output curve has been already observed and reported for many different device configurations and has sometimes been attributed to a lateral field dependent contact resistance.47-55 In Table 1, the critical device parameters Von (onset voltage), Vthr (threshold voltage), S (subthreshold swing), μlin (charge carrier mobility in the linear regime), and μsat (charge carrier mobility in the saturation regime) are compiled and averaged over eight devices for each transistor type. On average, C60-based OTFTs show a charge carrier mobility of 0.7 cm2 V−1 s−1 in the saturation regime, a threshold voltage of 1.3 V, and a small subthreshold swing of 305 mV dec−1. Pentacene-based OTFTs have on average a mean threshold voltage of −4.7 V, a very small subthreshold swing of 225 mV dec−1, and a field-effect mobility of 0.22 cm2 V−1 s−1 in the saturation regime. The gate leakage currents are very low and in the range of 10−10 A. The balanced performance of our p- and n-type OTFTs, as well as the fact that both transistor types strictly behave as normally off transistors at zero applied gate voltage is a good base for integrating them in complementary organic inverters. A schematic image of such a complementary inverter circuit is displayed in Figure 3a together with the voltage transfer characteristics (VTCs) of a typical device and the static gain measured for operation voltages of VDD = 4, 5, 6, and 7 V. The inverter exhibits extraordinarily high small-signal gains; for all operation voltages, gains above 500 V/V are measured with a maximum value of about 1000 V/V for VDD = 7 V. The best performing device even has a maximum gain value of 1600 V/V. Moreover, a very sharp transition regime (ΔVin ≤ 40 mV) and a full rail-to-rail swing are observed. The extracted inverter parameters are compiled in Table 2. The switching threshold voltages VM are found to be very close to the ideal value of VDD/2 at all operation voltages with a nearly perfect fit (e.g., VM = 2.04 V at VDD = 4 V). In Figure 3b, the mismatches of the threshold voltages to the ideal values (ΔVM) are plotted as a function of VDD revealing a linear increase of ΔVM with the supply voltage. This means that the asymmetry of the VTCs increase with increasing the operation voltages. Additionally, the noise margins (NM) are plotted in Figure 3b as a function of VDD, illustrating the linear decrease of the NM with increasing operation voltage. Such a behavior reveals the direct correlation between ΔVM and NM and is an indication of the deviation of the VTCs from perfect symmetry. The noise margin is an important figure of merit of an inverter stage and measures the immunity against inevitable transistor parameter variations and electrical noise.56 There are several ways to determine the noise margin of an inverter. One convenient way is called the “maximum equal criterion” (MEC), where the NM is found by the maximum square that fits between inverter transition curve and the mirrored inverter curve as shown in Figure 3c.22, 35 The NM values for all the supplied voltages are listed in Table 2. The noise margin is mainly limited by the steepness of the transition ΔVin and the position of the switching threshold voltage VM (VM = Vin = Vout) as shown in Figure 3c. High and balanced noise margins are found when the ideal condition VM = VDD/2 is met, thus when VM = Vin =VDD/2 = Vout. The inverter in Figure 3c has a NM of 1.79, which is 90% of the maximum theoretical value for a supply voltage of 4 V, determined by the “maximum equal criterion.” Additionally, the “negative slope criteria” reveals a balanced NM of 1.85 V (92.5%) for a supply voltage of 4 V. The OTFTs with pentacene and C60 semiconductor layers (as used in the complementary inverters) were also analyzed with regard to their long-term stability. The dependence of their onset voltage and charge carrier mobility on the time period after preparation is plotted in Figure 4 based on measurements of at least five devices for each transistor type. The error bars display the standard deviations. p- and n-type devices exhibit an onset voltage shift of +1.3 and +0.95 V, respectively, over a period of 45 days. The main part of the shift occurred either after the first or after the second measurement and then the onset voltage shift tended to saturate. It seems that both pentacene- and fullerene-based devices stabilized their electrical properties after few days. Between day 8 and day 45 no significant change in the transfer characteristics was observed. Concerning the subthreshold swing, no significant change was observed over 45 days (S = 215 mV dec−1 (0 days), 210 mV dec−1 (8 days), and 225 mV dec−1 (45 days)) in the pentacene OTFTs, indicating that the interface trap density is stable. On the contrary, after 8 days an increase of the swing was observed for the C60 devices from 305 mV dec−1 (0 days), to 410 mV dec−1 (8 days), to 430 mV dec−1 (45 days). The mean value of the charge carrier mobility of the pentacene OTFTs showed no significant variation over 45 days: 0.22 cm2 V−1 s−1(fresh sample), 0.19 cm2 V−1 s−1 (after 8 days), 0.21 cm2 V−1 s−1 (after 45 days). In contrast, a strong reduction of about one order of magnitude (from 0.7 to 0.06 cm2 V−1 s−1 within the first 8 days and to 0.05 cm2 V−1 s−1 after 45 days) was observed for the fullerene transistors. In order to test the reliability of our OTFT devices we have also performed negative and positive bias stress tests. The bias stress was done 1 day after fabrication, on devices which had been previously measured only once. A reversible negative onset voltage shift of about 400 mV was observed under negative bias of −7.5 V over 21 hours stress (see Figure 5a,b) The main part of the negative voltage shift occurred during the first 2 hours (300 mV) whereas shift saturation was reached after 6 hours. The positive bias stress resulted in a significantly smaller positive onset voltage shift (ca. +100 mV over 4 hours stressing the device). Devices that were stored for seven months in the glovebox showed no bias stress effect at all (i.e., shift of the onset voltage) when their transistor characteristics were measured at regular intervals during the storage period. In order to investigate the “long-time” behavior of complementary inverters, electrical measurements were done after 1, 4, 8, and 45 days of the respective device preparation. Inverters were measured 1 day after device stabilization (see Figure 4a,b). The “long-time” behavior of complementary inverters is shown in Figure 4c,d where the VTC and gain curves are plotted as a function of time. For the lowest VDD of only 4 V, a small shift of the switching threshold voltage was measured: starting from 2.04 V after 1 day to an identical value of 2.17 V after 8 and 45 days, respectively, with a related exceptional high noise margin of 1.79 V (90% of the theoretical maximum) after 1 day and 1.74 V (87%) after 8 and 45 days. It is interesting to note that, after 8 days of storage time, the hysteresis in inverter characteristics was virtually negligible (<100 mV, see Figure 4d) and moreover, repeated measurements did not change the inverter transition, although the gain was somewhat reduced (from 503 (0 days) to 320 (8 days) and 195 (45 days)). The operational stability of the VTC was shown over a period of at least 45 days (Figure 4c for VDD = 4 V). Furthermore, the remarkable long-term stability of these TMSC-based complementary inverters was demonstrated by 16 consecutively recorded inverter curves that are virtually superimposed over one another (Figure 5c). The current–voltage characteristics show that the Al2O3 + TMSC bilayer capacitors have substantially lower leakage currents than the single TMSC layer devices. Due to the roughness of the aluminum bottom electrode with spikes up to 10 nm, the anodization process is a convenient method to reduce the leakage currents for at least three orders of magnitude at an electric field of 3 MV cm−1 as displayed in Figure 1d and make the dielectric layer more robust.57 Another advantage of the anodization step is the substitution of the hydroxide of the native oxide layer. Finally, the subsequent short oxygen plasma treatment (see the Experimental Section) is sufficiently removing all residuals left after the anodization process. This procedure allows for the generation of a pure and trap-reduced dielectric interface to the organic semiconductors, verified by C(f) measurements at low frequencies, revealing a virtually flat permittivity in the mHz to kHz frequency range and low dielectric losses which both are indicative of a high purity and negligible amount of mobile ionic species. The generation of this excellent interface is subsequently reflected in obtaining virtually hysteresis-free characteristics of all the fabricated OTFTs. One important factor that often influences the performance of polycrystalline OTFTs, and here in particular the charge carrier mobility, is the size of the crystallites.58, 59 As shown by several groups, the ratio of the surface energy of the substrate to that of the molecules is one important factor determining the growth mode.60-63 For a low surface energy material with a smooth surface like TMSC, a Volmer–Weber growth mode is expected, and accordingly 3D islands with a rather high nucleation density and small grain sizes (150–300 nm) are formed (see Figure 1a).64 The resulting high density of grain boundaries may cause a significant decrease of the charge carrier mobility, since grain boundaries may act as charge trapping sites.59 On the other hand, a better interconnectivity between pentacene grains on low surface energy materials like TMSC with less voids and better contacts may reduce the number of trap states thus promoting the mobility of charge carriers in the channel.59, 61 In general, there is an interplay between grain boundary related traps and interface traps with regard to their influence on charge carrier mobility. The low subthreshold swing observed in all our pentacene-based OTFTs is indicative of a low interface trap density which balances the detrimental influence of the large grain boundary trap density on the overall charge carrier mobility.65 Accordingly, a reasonable mobility around 0.2 cm2 V−1 s−1 is observed in the p-type devices. In C60 films, the influence of molecular ordering on the charge carrier mobility is by far not as significant as in pentacene films, which is attributed to the complete isotropy of the fullerene molecule.66 In the pentacene OTFTs (see Figure 2b), a non-linear current increase in the linear regime (|VDS| < |VGS − Vthr|) of the ID(VDS) output characteristics is observed, especially at higher gate bias. Several mechanisms have been discussed in literature to understand such a non-linearity, which primarily can be observed in staggered bottom gate devices.67 The proposed explanations include: i) the anisotropy of the charge carrier mobility for thick semiconductor films,68 ii) common gate-induced parasitic currents that hinder the accumulation of the mobile charges by forming an effective potential barrier under the drain contact,47 and iii) large barrier heights at the injecting electrode stemming from an energy misalignment between the work functions of contact material and semiconductor.48, 49, 54 Since neither thick semiconductor films, nor a common gate or large contact barriers are found in our devices, none of these mechanisms seem applicable here. However, it has been shown that a field-dependent mobility (often in combination with a small contact barrier) may result in a non-linear drain voltage dependence of the channel current due to Poole–Frenkel conduction.51-53 The latter originates from a (lateral) field-dependent emission of carriers from trap states and predicts a square-root dependence of ln(ID/VDS) on the drain voltage.51-53, 69-71 A respective plot of the pentacene output curve in Figure 5d indeed follows the Poole–Frenkel square-root dependence in the low-field regime 0.25 < VDS < 2 V, thus indicating that a field-dependent mobility has to be considered. The absence of any hysteresis in the I(V) curves and the low and stable value of the subthreshold swing reflect a low density of shallow acceptor-like interface traps in the pentacene OTFTs.72 Nevertheless, shallow traps are not responsible for the observed non-linearity and the field-dependence of the mobility.53 However, as pointed out by Di Carlo et al.,73 the polycrystallinity of the pentacene layer gives rise to grain-boundary-related deep traps which contribute to a field dependence of the charge carrier mobility. This is all the more likely, given that the pentacene grain sizes are 300 nm at most, hence meaning a fairly large density of grain boundaries. As revealed by Figure 4 the characteristics of both pentacene- and C60-based OTFTs show a positive onset voltage shifts upon storage which saturates after a couple of measurements. The virtually stable subthreshold swing (especially in pentacene OTFTs) as well as the negligible hysteresis exclude shallow traps as the origin of the shift. On the contrary, it seems that negatively charged (acceptor-like) deep trap states are responsible for the positive onset voltage shift in pentacene.59 These electron traps are filled either over time or during the first measurements by the applied positive gate bias. They cannot be easily discharged by the gate bias sweep and therefore are not contributing to the swing, but instead they generate the small onset voltage migration in pentacene-based OTFTs.72 It has been reported by many authors74 that the presence of humid air may induce the formation of deep acceptor-like trap states in pentacene (however, donor-like trap states may also be generated) due to defect molecules such as C22H15O (involving CHOH bond formation at the central fourfold coordinated carbon), C22H15 (involving a CH2 bond at the central carbon), or C22H13O (involving a CO bond at the central carbon).75 During fabrication and sample transfer from the evaporator to the measurement stage humid air diffuses into the semiconductor layer and may give rise to such chemical reactions. For instance, oxygen diffusion can happen even if the devices are never exposed to ambient condition, but transferred directly and measured in a glovebox with reduced oxygen and water atmosphere. Hallam et al.76 have also observed that the reaction of oxygen with pentacene is strongly facilitated in the hole-accumulation mode, meaning that these traps are preferably generated under device operation with the presence of some oxygen (intercalated in the numerous grain boundaries, etc.). We observed that the storage of inactive devices in air and their subsequent measurement in vacuum did not induce a change in their I(V) characteristics. We also observed that the storage time prior to the first measurement has little influence on the device instability (i.e., on the onset voltage shift). However, in this model of oxygen-, hydroxyl-, and hydrogen-related gap states, the first measurement induces the formation of deep acceptor-like traps (due to the reaction of residual oxygen or hydroxyl with the pentacene's central carbon atoms), which then, in a second measurement, are filled by electrons. Moreover, also donor-like traps are generated which, however, are reaching not as deep in the band gap as the acceptor-like traps (see Northrup and Chabinyc75). This model provides an explanation for the positive shift of the onset voltage between first and second measurement (Figure 4a) and also for the fast saturation of the onset voltage shift in glovebox. In order to clarify which type of humid air induced defect states are present in our devices, we performed X-ray photoelectron spectroscopy (XPS) measurements on freshly prepared pentacene films (in situ), and after storage in humid air for 120 min (see Figure S2, Supporting Information). After storage under ambient conditions, a small increase of the COH bond at 286.5 eV binding energy is observed that can be attributed to the CHOH defect according to Northrup and Chabinyc.75 The quantitative analysis reveals an increase of the COH fraction from 0.2 to 1.2 at%. At the CO double bond position (288 eV) no change is detected. That implies that trap states in our devices (responsible for bias stress and the positive onset voltage shift) can mainly be attributed to CHOH defects. It should be mentioned that the absence of any mobility degradation in pentacene OTFTs argues against an impurity formation of pentacene quinone (where both central carbons are double bound to oxygen atoms).77 For the C60 transistors, one observes a strong decrease of the charge carrier mobility during 8 days of storage which is caused by oxygen-induced deep electron traps distributed all over the device (surface, grain boundaries, bulk, interface). This severe oxygen-sensitivity is a generally known degradation effect of fullerene.78 The decrease in charge carrier mobility and the shallow electron traps at the dielectric–semiconductor interface (note that the subthreshold swing is slightly increasing) result in a positive onset voltage shift of the C60 transistors. With respect to the complementary inverters, noise margin values beyond 78% from the maximum theoretical value for all supply voltages are excellent, and demonstrate the high operational robustness of the OTFT devices. At a very low supply voltage of 4 V, our bilayer dielectric-based organic complementary inverters have a static gain of more than 500 V/V with a noise margin of 92.5%, which is outperforming already reported devices with similar architecture (see the compilation of inverter performance given in ref. 38 and also refs. 24-40). Even gain values above 1000 V/V (record values up to 1600 V/V) were measured for our fabricated devices. This is all the most remarkable, as the charge carrier mobility values of the individual transistors are not particularly high, thus supporting the notion that the balance of the mobility values between p- and n-channel combined with the virtually non-existing hysteresis are the decisive factors for recording high gain and high noise margin values.28 Accordingly, a mobility ratio near 1 would be the optimum,42 otherwise, if the imbalance is not too high (imbalance ratio ≤ 10), it can be compensated by selecting n- and p-channel transistors with different geometry (W/L ratio).30, 36 In our case, the mobility imbalance ratio is around 4. The static gain, g, of a complementary inverter is predominantly determined by technology parameters, especially the channel length modulation parameters λn,p of both, p- and n-type transistors. A good matching of these parameters (visible through a good saturation of both output curves) can lead to a significant increase of the gain values. A detailed explanation is shown in the Supporting Information. Furthermore, high gain values are also determined by the dielectric–semiconductor interface itself. An insulator with an extremely low electron trap density (as this is the case for TMSC) is translated in having I(V) curves with virtually zero hysteresis. Accordingly, it is possible to perform measurements with a very high voltage resolution (high data rate meaning small voltage steps) thus enabling one to uncover the intrinsically high gain value of the complementary inverter without masking it by hysteresis effects. The noise margin decreases with increasing VDD and, due to their strong correlation, this is also true for the symmetry of the VTCs (parameterized by ΔVM, see Figure 3b). A reason for this behavior can be found in the bias stress that was observed for both types of transistors. The negative shift of Von under negative gate bias, and the positive s