Flexible inkjet-printed dual-gate organic thin film transistors and PMOS inverters: Noise margin control by top gate

Abstract

Low operating voltage dual-gate p-type organic thin film transistors (OTFTs) and PMOS inverters have been fabricated on 125 μm-thick flexible polyethylene naphthalate (PEN) substrates by solution-processed techniques. Inkjet-printed silver electrodes are used for gate, source, and drain contacts while the active organic semiconducting material is printed by a dispenser system over parylene dielectric. Bottom channel, top channel, and dual-gate OTFTs separately display average charge carrier mobilities of 0.03, 0.11, and 0.37 cm 2 V −1 s −1 , respectively. Top-gate is used to independently tune the threshold voltage for bottom-gate OTFT and vice versa. Two PMOS inverters are fabricated with high gain and low supply voltage operation. Ideal symmetric voltage transfer characteristics with high noise margin are achieved by controlling the threshold voltage of the driver OTFT by top-gate bias for low supply voltage, V DD = −2.5 V. • Flexible low voltage dual-gate OTFTs are fabricated by inkjet printing technique. • Dual-gate OTFTs are characterized in bottom-, top-, and dual-gate mode. • V Th of bottom channel OTFT is linearly control by top gate and vice versa. • DLL and ZVLL, PMOS inverters are compared in terms of gain and noise margin. • Ideal PMOS inverters are achieved by controlling V Th of bottom OTFT by top gate.