Impact of channel thickness on device scaling in vertical InGaZnO channel charge-trap memory transistors with ALD Al2O3 tunneling layer

Abstract

This study investigates the impact of channel thickness (TCH) variation on memory performance and its physical origins in vertical channel charge trap memory (V-CTM) using InGaZnO (IGZO) channels for X–Y scaling. When the TCH decreased, the subthreshold slope (SS) increased from 0.21 to 0.30 V/dec, while the minimum program voltage decreased from 12 to 8 V, indicating a performance trade-off. The analysis of bulk trap density extracted by SS, density of states distribution, and x-ray photoelectron spectroscopy confirmed an increase in the number of trap states and hydrogen-related defects in the IGZO channel when a thin TCH is employed. As a result, it was expected that the barrier height at the active layer/TL would be lowered during program operations at relatively thin channel. However, the SS would also be degraded due to an increase in sub-gap states, such as OH- and VOH, induced by hydrogen incorporation. The V-CTM with an optimal TCH of 7 nm had a maximum memory window of 5.7 V. The program/erase states were maintained for 106 s before experiencing a 50 % charge loss, and 5-level memory states were verified to be available within a memory window of 3.2 V for 108 s with little degradation. It was noteworthy that the long-term reliability and multilevel implementation could be secured for the V-CTM with a TCH as thin as 7 nm, demonstrating the sound feasibility of its X–Y scaling. This work presents new key parameters and understanding of device integration issues for future 3D structured memory transistors, and aims to contribute to the advancement of memory technologies using oxide semiconductor channels.