Template-assisted Selective Epitaxy Research Articles

Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungsten.

3D integration of III-V semiconductors with Si CMOS is highly attractive since it allows combining new functions such as photonic and analog devices with digital signal processing circuitry. Thus far, most 3D integration approaches have used epitaxial growth on Si, layer transfer by wafer bonding, or die-to-die packaging. Here we present low-temperature integration of InAs on W using Si3N4 template assisted selective area metal-organic vapor-phase epitaxy (MOVPE). Despite growth nucleation on polycrystalline W, we can obtain a high yield of single-crystalline InAs nanowires, as observed by transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD). The nanowires exhibit a mobility of 690 cm2/(V s), a low-resistive, Ohmic electrical contact to the W film, and a resistivity which increases with diameter attributed to increased grain boundary scattering. These results demonstrate the feasibility for single-crystalline III-V back-end-of-line integration with a low thermal budget compatible with Si CMOS.

Growth of type I superlattice III-V heterostructure in horizontal nanowires enclosed in a silicon oxide template

Template assisted selective epitaxy (TASE) offers an attractive monolithic integration route for III-V semiconductors on Si, benefitting from reduced defect density and versatility in its employment to create various electronic and photonic devices. This work achieves compositional and morphological control of lattice matched InGaAs quantum wells embedded in a horizontal InP nanowire grown directly from a Si seed and of the respective heterointerfaces. A series of growth experiments introducing variations of the precursor switching sequence in the growth recipe, and a subsequent scanning transmission electron microscopy and energy dispersive X-ray spectroscopy analysis, were employed to create and characterize a type I superlattice enclosed in a silicon oxide template.

Electrodeposition as an Alternative Approach for Monolithic Integration of InSb on Silicon.

High-performance electronics would greatly benefit from a versatile III-V integration process on silicon. Unfortunately, integration using hetero epitaxy is hampered by polarity, lattice, and thermal expansion mismatch. This work proposes an alternative concept of III-V integration combining advantages of pulse electrodeposition, template-assisted selective epitaxy, and recrystallization from a melt. Efficient electrodeposition of nano-crystalline and stochiometric InSb in planar templates on Si (001) is achieved. The InSb deposits are analysed by high resolution scanning transmission electron microscopy (HR-STEM) and energy-dispersive X-ray spectroscopy (EDX) before and after melting and recrystallization. The results show that InSb can crystallise epitaxially on Si with the formation of stacking faults. Furthermore, X-ray photoelectron (XPS) and Auger electron (AE) spectroscopy analysis indicate that the InSb crystal size is limited by the impurity concentration resulting from the electrodeposition process.

In-Plane Monolithic Integration of Scaled III-V Photonic Devices

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

Hybrid III-V Silicon Photonic Crystal Cavity Emitting at Telecom Wavelengths.

Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality (Q)-factors and small mode volumes. Here, we demonstrate a novel concept of a one-dimensional hybrid III-V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III-V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III-V gain material. The III-V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate, and hence in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III-V/Si PhCs show emission over the entire telecommunication band from 1.2 to 1.6 μm at room temperature validating the device concept and its potential towards fully integrated light sources on silicon.

Monolithically Integrated Catalyst-Free High Aspect Ratio InAs-on-Insulator (InAsOI) FinFETs for pH Sensing

In this work, we report a novel Indium Arsenide-on-insulator (InAsOI) FinFET platform designed with record high aspect ratio that favors the use of the devices as charge sensors. InAs has very high mobility among III-V semiconductors and an intrinsic surface accumulation layer yielding good ohmic contacts thus making it an interesting choice for chemical and biological sensing platforms. Template Assisted Selective Epitaxy (TASE) enables the integration of III-V highly scaled devices, monolithically integrated on Silicon, within a fully CMOS compatible fabrication scheme hence without any catalyst-induced growth. With a new geometry, high-aspect-ratio (HAR) InAs fins and a new application of pH sensing the versatility of TASE is exhibited. HAR InAs fins, fin height to fin width in excess of 4 for fin width down to 30 nm are fabricated on a Si substrate. The HAR InAs-on-insulator fins are characterized as pH sensors. A sensitivity of 38.8 mV per pH is extracted at $6~\mu \text{A}$ drain current from a 40 nm wide 20 multi-finger array.

InP-on-Si Optically Pumped Microdisk Lasers via Monolithic Growth and Wafer Bonding

On-chip optical light sources are key components in photonic integrated circuits and optical communication. In this paper, we use a novel integration technique called template-assisted selective epitaxy (TASE) to monolithically integrate InP microdisk lasers on silicon. TASE offers several advantages for new device concepts such as lateral doping, dense co-integration of different III–V materials, and in-plane integration with silicon electronics and passive components. Here, we demonstrate room-temperature lasing from InP hexagonal microdisks integrated via TASE. In order to assess and evaluate the viability of TASE, a second InP hexagonal microdisk sample is prepared for comparison using the highly developed and mature direct wafer bonding technique. The lasing performance of the TASE monolithic devices and the bonded microdisk devices is investigated under pulsed optical pumping as a function of temperature and compared. The lasing threshold as well as the light-in light-out curves of our TASE structures compare favorably with the bonded InP hexagonal microdisks. This demonstrates that our TASE approach is a promising technique for the monolithic integration of optical devices on Si.

Microcavity Lasers on Silicon by Template-Assisted Selective Epitaxy of Microsubstrates

The vision of microchips that benefits from the high data rates of optical links has recently lead to novel concepts for the monolithic integration of active gain materials on silicon. In this letter, we use template-assisted selective epitaxy (TASE) for the monolithic integration of GaAs microsubstrates on silicon, which allows the subsequent integration of lattice-matched III-V laser cavities. We demonstrate the room-temperature operation of optically pumped microdisk-lasers with hexagonal top-facets and diameters as low as 1.2 μm. The devices exhibit uniform emission spectra, low lasing thresholds of P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> = 13.6 ± 0.7 pJ/pulse, and a high-temperature stability (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> = 370 K). Scanning electron microscope and photoluminescence analysis of larger devices with a flat top-facet reveal a rotation of the crystal orientation and further reduce lasing thresholds. Our results show that the monolithic integration of III-V microsubstrates on silicon offers a versatile platform for on-chip light sources with excellent optical properties.

Nanoscale analysis of electrical junctions in InGaP nanowires grown by template-assisted selective epitaxy

We report the analysis of the electrical properties of Inx−1GaxP nanowires (NWs) grown by template-assisted selective epitaxy. The individual NW properties are investigated by means of electron beam induced current microscopy (EBIC) and current-voltage curves acquired on single nano-objects. First, a set of samples containing n-doped InGaP NWs grown on a p-doped Si substrate are investigated. The electrical activity of the hetero-junction between the NWs and the substrate is demonstrated and the material parameters are analyzed, namely, the n-doping level is determined in relation to the dopant flow used during the growth. These results were used to design and elaborate InGaP NWs containing a p-n homo-junction. The electrical activity of the homo-junction is evidenced using EBIC mapping on single NWs, and material parameters (namely, the doping and the minority carrier diffusion lengths) for the p- and n-doped InGaP segments are estimated. Finally, the first proof of a photovoltaic effect from the NW homo-junctions is obtained by photocurrent measurements of a contacted NW array under white light irradiation.

Facet-selective group-III incorporation in InGaAs template assisted selective epitaxy

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities.

III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n+ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.

Concurrent Zinc-Blende and Wurtzite Film Formation by Selection of Confined Growth Planes.

Recent research on nanowires (NWs) demonstrated the ability of III–V semiconductors to adopt a different crystallographic phase when they are grown as nanostructures, giving rise to a novel class of materials with unique properties. Controlling the crystal structure however remains difficult and the geometrical constraints of NWs cause integration challenges for advanced devices. Here, we report for the first time on the phase-controlled growth of micron-sized planar InP films by selecting confined growth planes during template-assisted selective epitaxy. We demonstrate this by varying the orientation of predefined templates, which results in concurrent formation of zinc-blende (ZB) and wurtzite (WZ) material exhibiting phase purities of 100% and 97%, respectively. Optical characterization revealed a 70 meV higher band gap and a 2.5× lower lifetime for WZ InP in comparison to its natural ZB phase. Further, a model for the transition of the crystal structure is presented based on the observed growth facets and the bonding configuration of InP surfaces.

Dopant-Induced Modifications of Ga xIn(1- x)P Nanowire-Based p-n Junctions Monolithically Integrated on Si(111).

Today, silicon is the most used material in photovoltaics, with the maximum conversion efficiency getting very close to the Shockley-Queisser limit for single-junction devices. Integrating silicon with higher band-gap ternary III-V absorbers is the path to increase the conversion efficiency. Here, we report on the first monolithic integration of Ga xIn(1- x)P vertical nanowires, and the associated p-n junctions, on silicon by the Au-free template-assisted selective epitaxy (TASE) method. We demonstrate that TASE allows for a high chemical homogeneity of ternary alloys through the nanowires. We then show the influence of doping on the chemical composition and crystal phase, the latter previously attributed to the role of the contact angle in the liquid phase in the vapor-liquid-solid technique. Finally, the emission of the p-n junction is investigated, revealing a shift in the energy of the intraband levels due to the incorporation of dopants. These results clarify some open questions on the effects of doping on ternary III-V nanowire growth and provide the path toward their integration on the silicon platform in order to apply them in next-generation photovoltaic and optoelectronic devices.

Room-Temperature Lasing from Monolithically Integrated GaAs Microdisks on Silicon.

Additional functionalities on semiconductor microchips are progressively important in order to keep up with the ever-increasing demand for more powerful computational systems. Monolithic III–V integration on Si promises to merge mature Si CMOS processing technology with III–V semiconductors possessing superior material properties, e.g., in terms of carrier mobility or band structure (direct band gap). In particular, Si photonics would strongly benefit from an integration scheme for active III–V optoelectronic devices in order to enable low-cost and power-efficient electronic–photonic integrated circuits. We report on room-temperature lasing from AlGaAs/GaAs microdisk cavities monolithically integrated on Si(001) using a selective epitaxial growth technique called template-assisted selective epitaxy. The grown gain material possesses high optical quality without indication of threading dislocations, antiphase boundaries, or twin defects. The devices exhibit single-mode lasing at T < 250 K and lasing thresholds between 2 and 18 pJ/pulse depending on the cavity size (1–3 μm in diameter).

Observation of Twin-free GaAs Nanowire Growth Using Template-Assisted Selective Epitaxy

The continuous scaling of electronic devices has brought Si based Complementary-Metal –Oxide-Semiconductor (CMOS) technology close to its limits, requiring novel materials and approaches to increase performance. Group III-V semiconductor nanowires have evolved as promising candidates due to their superior carrier mobility, saturation velocity and capability for bandgap engineering and integration in heterostructures, as well as their potential for use in active photonic devices. However, CMOS compatible, epitaxial integration of III-Vs on Si(100) remains challenging, mainly due to the formation of crystal defects, significantly reducing device performance. Selective Area Growth (SAG)1,2 and epitaxial lateral overgrowth (ELO)3–5 have both been demonstrated to reduce defects due to lattice mismatch. In a more recent method referred to as Template-Assisted Selective Epitaxy (TASE)6–10 nanostructures are grown entirely within pre-defined hollow template cavities containing a small Si seed, thus minimizing the...

High-Mobility GaSb Nanostructures Cointegrated with InAs on Si

GaSb nanostructures integrated on Si substrates are of high interest for p-type transistors and mid-IR photodetectors. Here, we investigate the metalorganic chemical vapor deposition and properties of GaSb nanostructures monolithically integrated onto silicon-on-insulator wafers using template-assisted selective epitaxy. A high degree of morphological control allows for GaSb nanostructures with critical dimensions down to 20 nm. Detailed investigation of growth parameters reveals that the GaSb growth rate is governed by the desorption processes of an Sb surface layer and, in turn, is insensitive to changes in material transport efficiency. The GaSb crystal structure is typically zinc-blende with a low density of rotational twin defects, and even occasional twin-free structures are observed. Hall/van der Pauw measurements are conducted on 20 nm-thick GaSb nanostructures, revealing high hole mobility of 760 cm2/(V s), which matches literature values for high-quality bulk GaSb crystals. Finally, we demonstrate a process that enables cointegration of GaSb and InAs nanostructures in close vicinity on Si, a preferred material combination ideally suited for high-performance complementary III-V metal-oxide-semiconductor technology.

Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 1: Experimental Devices

Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with ION of a few μA/μm for |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> | = |V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> | = 0.5 V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS.

Underlap counterdoping as an efficient means to suppress lateral leakage in the electron–hole bilayer tunnel FET

The electron–hole bilayer tunnel (EHBTFET) has been proposed as a density of states (DOS) switch capable of achieving a subthreshold slope lower than 60mV/decade at room temperature; however, one of the main challenges is the control of the lateral band-to-band tunneling (BTBT) leakage in the OFF state. In this work, we show that by using oppositely doped underlap regions; the unwanted penetration of the wavefunction into the underlap region at low gate biases is prevented; thereby drastically reducing the lateral BTBT leakage without any penalty on the ON current. The method is verified using a full-quantum 2D Schrödinger–Poisson solver under the effective mass approximation. For a channel thickness of 10 nm, an EHBTFET with counterdoping can exhibit an ON-current up to and an average subthreshold swing (SS) of about 30 mV/dec. Compared to previous lateral leakage suppression solutions, the proposed method can be fabricated using template-assisted selective epitaxy.

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.

Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si

A comprehensive investigation of InAs epitaxy on silicon using template-assisted selective epitaxy is presented. The variation in axial growth rate of InAs nanowires inside oxide nanotube templates is studied as function of nanotube diameter (20–140 nm), growth time (0–30 min), growth temperature (520–580 °C), V/III ratio (40–160), nanotube spacing (300–2000 nm), and substrate crystal orientation. It is found that the effective V/III ratio is reduced at least by a factor of two within the nanotube templates compared to the outside, detectable by changes in the growth facet morphology. The reduced V/III ratio originates from the different transport mechanisms for the As and In precursor species; As and In species are both transported by Knudsen diffusion in the vapor, but an additional contribution of In surface diffusion reduces the V/III ratio. The results reveal the interplay of growth parameters, crystal facets and template geometry and thus are generally applicable for nanoscale selective epitaxy.