Abstract
It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.
Highlights
The integration of III-Vs on silicon is a long-standing goal because it would allow us to combine the attractive features of a low-cost, highly developed, and complex silicon platform with the added functionality of active photonic devices such as light sources and detectors
This is the case for lateralbasedcurrent-injection hybrid III‐V/Siarchitectures photonic crystal emitters which highlight the benefits of of locally
Our group demonstrated a novel concept for a one-dimensional hybrid IIIV/Si Photonic crystal (PhC) cavity, where we exploit template-assisted selective epitaxy (TASE) to replace the central parts of a Si PhC structure fabricated on SOI with III-V active materials [33]
Summary
The integration of III-Vs on silicon is a long-standing goal because it would allow us to combine the attractive features of a low-cost, highly developed, and complex silicon platform with the added functionality of active photonic devices such as light sources and detectors. The most common method for advanced integrated photonic applications is the directwafer bonding of a III-V wafer or individual III-V components on top of a Si wafer [3,4,5,6] This allows to grow the appropriate stack of III-V material lattice matched on a III-V carrier wafer, which may subsequently be recycled. 3 of the desirable in-plane or lateral doping profile for the placement of electrical contact can be implemented for all the above methods in additional steps, either through the consecutive regrowth of III-V material on both sides or by ion implantation This is the case for lateralbasedcurrent-injection hybrid III‐V/Siarchitectures photonic crystal emitters which highlight the benefits of of locally [27] and might be suitable for the implementation p- and placing gain material.
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