Observation of Twin-free GaAs Nanowire Growth Using Template-Assisted Selective Epitaxy

Abstract

The continuous scaling of electronic devices has brought Si based Complementary-Metal –Oxide-Semiconductor (CMOS) technology close to its limits, requiring novel materials and approaches to increase performance. Group III-V semiconductor nanowires have evolved as promising candidates due to their superior carrier mobility, saturation velocity and capability for bandgap engineering and integration in heterostructures, as well as their potential for use in active photonic devices. However, CMOS compatible, epitaxial integration of III-Vs on Si(100) remains challenging, mainly due to the formation of crystal defects, significantly reducing device performance. Selective Area Growth (SAG)1,2 and epitaxial lateral overgrowth (ELO)3–5 have both been demonstrated to reduce defects due to lattice mismatch. In a more recent method referred to as Template-Assisted Selective Epitaxy (TASE)6–10 nanostructures are grown entirely within pre-defined hollow template cavities containing a small Si seed, thus minimizing the...