Technology Node Research Articles

Exploring the impact of shrinking feature sizes on proton-induced saturation SEU cross-section through simulation

In the study reported here, Monte Carlo simulations were used to investigate single-event upsets (SEUs) induced by ultra-high-energy proton irradiation in electronic devices made with various technology nodes, and the simulation results show the following. For smaller technology nodes, the SEU cross section tends to increase when the incident proton energy exceeds 200 MeV, and the dependence of the SEU cross section on 200-MeV protons as a saturation point for technology nodes smaller than 90 nm might result in underestimated error rates. Finally, using proton SEE cross section data with energies higher than 200 MeV can better assess the severity of the non-saturation effect, and can also obtain more realistic error rate.

Robots, AI, and the Metaverse: Distinguishing the Intelligent Images in Science Fiction Movies

ABSTRACT The metaverse represents a significant leap forward in the creation of immersive and intelligent imagery. The evolution of intelligent imagery in sci-fi movies is characterized by the emergence, development, and convergence of various technological nodes. These nodes are not isolated from one another but rather represent iterative and intersecting dimensions of a larger whole. Meaningful integration of these elements requires thoughtful consideration of the intersections between the artificial intelligence image in the material world and that which is situated within virtual digital environments such as the metaverse. Thus, the integration of these disparate elements is a crucial step towards the development of a cohesive and advanced technological landscape within the realm of sci-fi filmmaking. To fully appreciate the role of intelligent imagery in science fiction movies, it is essential to examine the artistic image of robots in-depth, which remains one of the most integral components of the genre. Furthermore, the virtual and digitized nature of the metaverse means that artificial intelligence in this realm is disembodied, existing only as intelligent programmes. This unique feature has led to the emergence of general artificial intelligence in the metaverse.

Characteristics of inorganic acid emission from various generation semiconductor manufacturing factories

With advancements in semiconductor industry technology, the gas emissions per wafer have decreased, but the emission compositions have shown significant differences. This study analyzed nine semiconductor plants representing different generations of process technologies, ranging from 3 μm to 12 nm technology nodes. Stack inspections were conducted on the acid, alkali, and organic exhaust systems to understand the characteristics of inorganic acid emissions in plants in different process technologies. The analysis showed that with technological process and air pollution control equipment advancements, the emissions of inorganic acids per wafer decreased by 38% compared to the first generation. It is worth noting that both hydrofluoric acid and nitric acid are identified as the primary pollutants in traditional semiconductor process plants. At the same time, H2SO4 was instead the primary pollutant in advanced process plants. Based on these characteristics, each plant has established relevant improvement strategies. After two years of improvement, the emissions of inorganic acids per wafer in each generation of plants are evidenced to have further decreased by 15–56%. Hence, it is shown that these initiatives and studies have successfully helped to reduce air pollution emissions and promote advanced green manufacturing.

Assembly Solutions for Cost-Effective Heterogeneous Integration with Disparate Die Types

The semiconductor industry is driving to enable high volume integration of disparate die types via Heterogeneous Integration. These die can come from a range of wafer sizes fabricated in different technology nodes. This emerging package type creates new challenges regarding assembly efficiency and yield. Traditionally, flip-chip assembly process flows have utilized a single placement tool for the placement of the single die type onto the target substrate. For applications with multiple die types, a series of placement tools have been configured in a production line, with each tool dedicated to the placement of a specific die type. This paper and presentation explore the implications of this type of solution in the era of Heterogeneous Integration. Impacts on product yield, throughput, manufacturing efficiency, and overall cost of assembly will be explored for a broad range of Heterogeneous Integration die configurations. Based on a sensitivity analysis for the range of die types expected in these applications, a novel approach to optimization of overall assembly economics will be proposed. Appropriateness of this novel approach will be explored for a range of packaging solutions, including Flip Chip, 2.5D, 3D, and Fan-Out.

NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications

This paper presents the detailed analysis of n-channel Negative Capacitance Cylindrical Gate All Around Field Effect Transistor (NC-CGAAFET) of class Metal-Ferroelectric-Insulator Semiconductor (MFIS) at 2 nm technology node and its comparison with CGAAFET (Cylindrical Gate All Around Field Effect Transistor). NC-CGAAFET shows better performance in terms of ION, Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), and ION/IOFF when compared to CGAAFET. Further, NC-CGAAFET is analyzed at different values of ferroelectric layer thickness (TFE), along with different values of spacer dielectric constant (K), spacer length (LSP) and nanowire diameter (DNW) and found that SS goes below Boltzmann's limit (60 mV/dec) and further decreases with increasing TFE. Also observed that Negative-DIBL increases as TFE increases. In addition to this, the device is optimized for NDR (Negative Differential Resistance) free operation, to be applicable for both analog and digital applications, by varying TFE. The optimized NDR free NC-CGAAFET offers SS of 59.33 mV/dec, DIBL of 13.91 mV/V, and the ION/IOFF ratio of 3.28x higher than conventional CGAAFET by operating at low power supply (VDD ∼ 0.65V).

On-chip ESD Protection Design Methodologies by CAD Simulation

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

A Machine Learning-Based Short-Circuit Power Prediction at Floorplan Stage of IC Physical Design

This work is devoted to the study of the use of machine learning (ML) to predict short-circuit power consumption at the floorplan stage of the physical design of integrated circuits. The study was carried out for 4 cell groups: registers, combinational cells, sequential cells, and cells included in the clock network. An Arithmetic Logic Unit was selected and designed to create a database necessary for the training and testing of ML models. The design is carried out for various combinations of parameters. Input parameters for training models are supply voltage, temperature, clock frequency, library type based on threshold voltage, block utilization and block aspect ratio. The output parameters are the values of short-circuit power after gate level simulation, considering the parasitic parameters. In total, five algorithms were tested: Polynomial Regression, Decision Tree Regression, Random Forest Regression, Supported Vector Regression (SVR) and Multi-layer Perceptron (MLP). Root Mean Squared Error, R2 and Mean Absolute Percentage Error (MAPE) metrics were used to evaluate the performance of the models. The MLP showed the best performance, but the SVR algorithm with standardization of output parameters showed similar results with significantly less training time. The MAPE value for registers is » 0,89 %, for combinational cells » 3,19 %, for sequential cells » 2,42 % and for the clock network cells » 9,55 %. The proposed method of model training is not based on any technology-dependent data, which makes it universal for different technology nodes. The disadvantage of the method is the need for implementation of the whole design flow for a selected design with the selected range of parameters for collecting necessary training data, which requires additional time and machine resources.

Evaluation of dual-ONOFIC method for subthreshold leakage reduction in domino circuit

ABSTRACT A novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique.

High-density Fan-Out Chip on Substrate using M-Series (TM) and Adaptive Patterning® Technology

As silicon technology nodes advance and wafer costs increase, there is a strong incentive to shrink die size and concurrently, die pad pitch. This increased density typically drives higher cost advanced substrates with finer lines and spaces and potentially more layers. As a result of recent constraints on the substrate supply chain, this creates serious availability and cost concerns. A compelling solution is to use fan-out on substrate technology to increase the effective die pad pitch, allowing the use of simpler, lower layer count substrates. ASE used this single die Fan Out Chip on Substrate (FOCoS) approach in engineering and qualification builds starting in 2017 with a traditional fan-out solution. However, with increasing interconnect density, the conventional approach is limited in its ability to work with small bond pad pitches as the die shift during molding creates challenges for manufacturing. An oversized capture pad is often utilized to accommodate this shift and in one prominent case, an additional Cu layer is required. M-series’ use of Adaptive Patterning eliminates the need for oversized capture pads through a unique design-during-manufacturing process which precisely aligns the package interconnect layers to the actual location of each die after molding. This paper will examine the design and manufacturing of a FOCoS package using 4nm silicon through the cooperation of Deca and ASE. The design fans out the interface of a 12mm x 12mm die with 6,000 IO using a single RDL layer and 5 µm line and space. The die has a core pitch of 150µm with an average periphery pitch of 90µm. The resultant M-series flip-chip bumps have a core pitch of 150µm over 75% of the die area with a secondary pitch of 212µm encompassing the remaining perimeter of the die and the 30% body size growth provided by the fan-out region. The relaxed pitch provided by M-series fan-out opens the possibility to use the most cost-effective, readily available type of laminate substrate.

Two-dimensional semiconductors based field-effect transistors: review of major milestones and challenges

Two-dimensional (2-D) semiconductors are emerging as strong contenders for the future of Angstrom technology nodes. Their potential lies in enhanced device scaling and energy-efficient switching compared to traditional bulk semiconductors like Si, Ge, and III-V compounds. These materials offer significant advantages, particularly in ultra-thin devices with atomic scale thicknesses. Their unique structures enable the creation of one-dimensional nanoribbons and vertical and lateral heterostructures. This versatility in design, coupled with their distinctive properties, paves the way for efficient energy switching in electronic devices. Moreover, 2-D semiconductors offer opportunities for integrating metallic nanoribbons, carbon nanotubes (CNT), and graphene with their 2-D channel materials. This integration helps overcome lithography limitations for gate patterning, allowing the realization of ultra-short gate dimensions. Considering these factors, the potential of 2-D semiconductors in electronics is vast. This concise review focuses on the latest advancements and engineering strategies in 2-D logic devices.

Implementation of Background Calibration for Redundant FLASH ADC

Flash converters are suitable analog-to-digital converter architectures for high-speed applications. However, the benefits in terms of the frequency of smaller technology nodes are hampered by variability, which necessitates the use of large transistors. Comparator redundancy was introduced to overcome this trade-off; the best comparators were selected upfront (either at start-up or in the factory), and the unused comparators could be switched off. This work studies the possibility of performing comparator selection in the background concurrently with normal conversion to increase the converter lifetime. Thus, the system can automatically recover its performance from drifts or failures due to aging, temperature, etc. This paper proposes an embedded solution that includes a calibration stimulus generator (which only requires some external passive elements) and develops system design requirements. In addition, mathematical equations and error sensitivities of the system elements were derived. A 6b flash converter is implemented in UMC180nm technology, and transistor-level simulations of the system are provided to demonstrate the feasibility of the proposed system.

Insights into the impact of random dopant fluctuation on ferroelectric germanium source vertical TFET

This paper investigates the effect of random dopant fluctuation (RDF) on the performance of ferroelectric Germanium source vertical tunnel field effect transistor (FE GeS-vTFET) using 3-D device simulation. The variation in the on-state current (σION), off-state leakage current (σIOFF), current ratio σ(ION/IOFF), subthreshold swing (σSS), threshold voltage (σVTH), total gate capacitance (σCgg), transconductance (σgm) and cut-off frequency (σfT) for different source doping concentration and source thickness due to the effect of RDF are evaluated. The findings indicate an increasing tendency in RDF with higher doping concentration in the source region. The variation in the on-current is from 0.2173 mA to 0.2337 mA (∼1.075 times higher), and σIOFF varies from 4.939 fA to 16.545 fA (∼3.349 times higher) from 1 × 1020 /cm3 to 3 × 1020 /cm3 doping concentration, respectively for Germanium source thickness of 12 nm. RDF within the source region mainly contributes to the threshold voltage variation of about 92 % in all regions. The randomized dopant-induced σVTH for the FE GeS-vTFET compared with other field effect transistors of the same technology node showed a substantial reduction in σVTH, signifying that the device is more immune to the effects of RDF. Furthermore, the effect of temperature on the switching properties of the FE GeS-vTFET has been studied.

Performance Investigation of FinFET Structures: Unleashing Multi-Gate Control through Design and Simulation at the 7 nm Technology Node for Next-Generation Electronic Devices

In this manuscript, we outline a original study that represents the first investigation of its kind, focusing on DC and analog/RF performance of structural flavors of FinFET. A total of six structural variations (D1 to D6 devices) in FinFET as per the IRDS 7 nm technology node specifications is explored here. Through extensive simulations, our findings demonstrate that the incorporation of gate stack, spacer, and source/drain extension concepts in FinFETs leads to superior performance. The DC performance analysis produced near-ideal SS (∼65 mV dec−1) performance, lower leakage currents, improved switching performance, and reduced DIBL values for D3 to D6 devices owing to the incorporation of gate stack, spacer integration, and source/drain extension doping. In terms of analog/RF performance, the best suitable device is found to be D4 device having designed with 1017 cm−3 n-type lightly doped source/drain regions, spacer, and gate stack integrations. A significant improvement such as higher gm, reduced gd, enhanced AV, improved fT, GFP, GTFP, and TFP are obtained for D4 device marking a breakthrough in the FinFET designing. Overall, the findings contribute to the advancement of FinFET at 7 nm technology node, opening up new opportunities for applications in various electronic systems demanding improved device performance.

Tri-gate junctionless transistors with electrostatically highly doped channel

Multiple-gated junctionless transistors (JLTs) with an extremely simple structure and bulk-conduction-based operation could overcome fundamental problems with respect to short-channel effects for sub-3-nm technology nodes. In this paper, the performance of a tri-gate JLT with an electrostatically highly doped channel is demonstrated through numerical simulation. Unique characteristics previously reported in fabricated JLTs were exhibited by the tri-gate transistors with an additional bottom-gate bias (Vgb = 50 V), which induced an effectively highly doped state of the channel. The results of this study show the feasibility of producing impurity scattering-free JLTs for next-generation technology nodes.

VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques

Logic locking is a well-known solution that thwarts design intellectual property (IP) piracy and prevents illegal overproduction of integrated circuits (ICs) against adversaries in the globalized supply chain. The widespread prevalence of reverse-engineering tools, probing, and fault-injection equipment has given rise to physical attacks that can undermine the security of a locked design. Fault-injection attacks, in particular, can extract the secret key from an oracle, circumventing the defense offered by logic locking. When design IP is compromised through physical attacks, fixing corresponding vulnerabilities generally require a silicon re-spin, which is impractical under constrained time and resources. Thus, there is a requirement for a detection tool that can perform a pre-silicon evaluation of locked designs to notify the designer of any vulnerabilities that can be exploited using faults. In this work, we propose VIGILANT, a first-of-its-kind vulnerability detection tool against fault-injection attacks targeting the hardware implementation of locking techniques. More specifically, VIGILANT aids designers in identifying critical nets susceptible to fault-injection attacks. VIGILANT analyzes the underlying locked design and computes a list of candidate nets along with their fault values required for key leakage and consequently validates each candidate net as vulnerable or not, using a functional simulation model of the design (acting as an oracle). We showcase the efficacy of VIGILANT on different locked designs for four different locking techniques under various parameters such as technology nodes, layout-generation commands, and key-sizes. The accuracy of VIGILANT in identifying and validating all the candidate nets that are vulnerable to fault-injection attacks is 100%

Study of the Reliability for the Leakage Mitigation Methods using FinFETs

Introduction: In the very large-scale integration (VLSI) industry, scaling plays an important role in providing compact size and high-speed digital circuits. The major drawbacks faced by logic circuits are power dissipation and process, voltage, and temperature (PVT) variations. In the VLSI industry, the prediction of variability tolerance capability is mandatory to know the future performance of the circuits. The impact of PVT variation is large in nanoscale logic circuits and it has the power to alter the output characteristics of any logic circuit. The reasons that cause PVT variations are manufacturing defects, environmental conditions, and mishandling issues. Aims and Objective: This paper aims to discuss the process variations and briefly describe the previous work related to variability and various factors involved in PVT simulations. It also provides the idea of Monte-Carlo simulation in the Cadence Virtuoso tool. Methods: In this paper, the impact of PVT variations on different fin-shaped field effect transistor (FinFET) circuits was evaluated using the Cadence Virtuoso tool. Monte-Carlo simulation was performed on various leakage reduction techniques for the domino logic with the help of a multi-gate predictive technology model (PTM) FinFET at a 16nm technology node. Results: The footer-less domino logic (FLDL) circuit is designed and simulated using different leakage reduction techniques for reliability analysis. Conclusion: Cascaded leakage control transistor (CLCT) approach shows 81.75%, 67.83%, and 51.25% less statistical mean value for power dissipation as compared to conventional, on-off logic (ONOFIC), and alternative ONOFIC approaches in the case of FLDL OR2 logic circuit, respectively.

MDCIM: MRAM-Based Digital Computing-in-Memory Macro for Floating-Point Computation with High Energy Efficiency and Low Area Overhead

Computing-in-Memory (CIM) is a novel computing architecture that enormously improves energy efficiency and reduces computing latency by avoiding frequent data movement between the computation and memory units. Currently, digital CIM is regarded as more suitable for high-precision operations represented in floating-point arithmetic, as it is not limited by the bit width of ADC/DAC in analog CIM. However, the development of DCIM still faces two problems: On the one hand, mainstream SRAM-based DCIM memory cells introduce large area overheads, which contain at least six transistors per cell. On the other hand, existing DCIM solutions can only support the computing precision up to FP32, failing to meet the demands of high-accuracy application scenarios. To overcome these problems, this work designs a novel SOT-MRAM-based digital CIM macro (MDCIM) with higher area/energy efficiency and achieves double-precision floating-point (FP64) computation with a modified fused multiply–accumulate (FMA) module. The proposed design is synthesized with a 55 nm CMOS technology node, achieving 0.62 mW power consumption, 26.9 GOPS/W, and 0.332 GOPS/mm2 energy efficiency at 150 MHz with 1.08 V supply. Circuit level simulation results show that the MDCIM can achieve higher area utilization compared to previous SRAM-based CIM designs.

Improved Stability for Robust and Low-Power SRAM Cell Using FinFET Technology

In the current nanoscale regime, fin field effect transistor (FinFET) technology overcomes the limitations of metal oxide semiconductor field effect transistor (MOSFET) technology. Robust and low-power static random access memory (SRAM) design is a demanding task for memory designers, especially in the nanoscale regime. Therefore, this paper proposes a 10 transistor (10T)-based SRAM cell design using low-power FinFET technology. The proposed approach not only reduces the leakage current, but also improves cell stability in different states. The proposed SRAM cell is simulated and analyzed at a 10[Formula: see text]nm technology node using a multi-gate predictive technology model (PTM) for the transistors with a power supply of 0.7[Formula: see text]V. The comparison analysis is also presented with the existing designs. The read and write static noise margins, and SRAM electrical quantity matrix (SEQM) of the proposed SRAM cell are improved by 3.54×, 1.71× and 26.41×, respectively, compared with the conventional 6T (C6T) design. The reliability investigations and comparison of the proposed SRAM cell have been carried out using Monte Carlo simulations with [Formula: see text]% deviations in the process parameters. The reliability analysis shows that the proposed SRAM cell is less sensitive to process variations.

A single ended, single port configuration based 9 T SRAM cell for stability enhancement

The growing demand for power efficient devices and high-density memories has pushed researchers to develop low power SRAMs. The main objective for these researches is to reduce power consumption and enhances battery life and scaling of technology node. Consequently, in this paper a 9T SRAM bit cell with enhanced stability and single ended, single port configuration is proposed. The cell is designed and simulated at 180 nm technology node with a voltage supply of 1V. The cell proposed has low power consumption owing to single bitline, higher read stability due to isolated read port, better write margin due to disconnected feedback connection and resistant to soft errors because of half select disturbance free architecture. To assess the performance of the proposed cell its performance is compared against existing 6T, 8T, 9TST, SB 9T, TRD 9T, and NTV 9T bit cells. The HSNM (RSNM) and WM values for the proposed cell are equal to 364 mV and 378 mV respectively. The cell is designed to be half select disturbance free and supports bit interleaving. The reliability of the proposed cell is further analysed for local, global and temperature variation. While, the area footprint for the cell is 24.91 μm2.

Single event transient of SOI FinFET with total ionizing dose irradiation

Total ionizing dose (TID) irradiation impacts the device leakage currents or threshold voltage, which affects the single event transient (SET) vulnerability of electronics under radiation environment. SET response of SOI FinFET at 14 nm technology node after TID exposure is carried out at different dose level. Results show that the drain current peak presents a slight fluctuant with total dose, while the collected charge and the bipolar amplification coefficient first decrease with total dose and then increase. The potential reason is also discussed from competing mechanisms associated with decreasing threshold voltage from TID irradiation and increasing the drain diffuse current from the potential of the channel.