Technology Node Research Articles

Data-cell-variation-tolerant triple sampling non-destructive self-reference sensing scheme of STT-MRAM

Inevitable process variations (PVT) brought by both the magnetic tunneling junction (MTJ) and MOSFET based on the complementary metal-oxide semiconductor (CMOS) technology become a major obstacle for the mass production of spin transfer torque magnetic random access memory (STT-MRAM). The detriment of the process variations leads to a serious degradation in the fundamental yield with the shrinkage of the technology nodes. However, the conventional data-cell-variation-tolerant (DCVT) sense scheme cannot get the target read yield due to the limited sense margin (SM). To resolve this problem, a DCVT triple sampling non-destructive self-reference sensing scheme (TSNS) is proposed in the paper, which doubles the SM, with lower power consumption and better SM compared with the conventional DCVT sense scheme. Monte Carlo simulation with industry-compatible 65-nm model parameters results show that the proposed sensing scheme shows over 2.5 times higher SM and less power consumption compared to the previous self-reference circuit. The proposed sensing scheme can get the target read yield with lower power consumption.

A Linear Multi-Band Voltage-Controlled Oscillator with Process Compensation for SerDes Applications

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance.

Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network.

As the architecture of logic devices is evolving towards gate-all-around (GAA) structure, research efforts on advanced transistors are increasingly desired. In order to rapidly perform accurate compact modeling for these ultra-scaled transistors with the capability to cover dimensional variations, neural networks are considered. In this paper, a compact model generation methodology based on artificial neural network (ANN) is developed for GAA nanosheet FETs (NSFETs) at advanced technology nodes. The DC and AC characteristics of GAA NSFETs with various physical gate lengths (Lg), nanosheet widths (Wsh) and thicknesses (Tsh), as well as different gate voltages (Vgs) and drain voltages (Vds) are obtained through TCAD simulations. Subsequently, a high-precision ANN model architecture is evaluated. A systematical study on the impacts of ANN size, activation function, learning rate, and epoch (the times of complete pass through the entire training dataset) on the accuracy of ANN models is conducted, and a shallow neural network configuration for generating optimal ANN models is proposed. The results clearly show that the optimized ANN model can reproduce the DC and AC characteristics of NSFETs very accurately with a fitting error (MSE) of 0.01.

Multi-objective and multi-solution source mask optimization using NSGA-II for more direct process window enhancement.

Source and mask optimization (SMO) technology is increasingly relied upon for resolution enhancement of photolithography as critical dimension (CD) shrinks. In advanced CD technology nodes, little process variation can impose a huge impact on the fidelity of lithography. However, traditional source and mask optimization (SMO) methods only evaluate the imaging quality in the focal plane, neglecting the process window (PW) that reflects the robustness of the lithography process. PW includes depth of focus (DOF) and exposure latitude (EL), which are computationally intensive and unfriendly to gradient-based SMO algorithms. In this study, we propose what we believe to be a novel process window enhancement SMO method based on the Nondominated Sorting Genetic Algorithm II (NSGA-II), which is a multi-objective optimization algorithm that can provide multiple solutions. By employing the variational lithography model (VLIM), a fast focus-variation aerial image model, our method, NSGA-SMO, can directly optimize the PW performance and improve the robustness of SMO results while maintaining the in-focus image quality. Referring to the simulations of two typical patterns, NSGA-SMO showcases an improvement of more than 20% in terms of DOF and EL compared to conventional multi-objective SMO, and even four times superior to single-objective SMO for complicated patterns.

Compact Spice Models for Terafets

Field effect transistors (FETs) in plasmonic regimes of operation could detect terahertz (THz) radiation and operate as THz interferometers, spectrometers, frequency-to-digital converters and THz modulators and sources. We report on the development of compact models for Si MOS (Metal-Oxide-semiconductor) and heterostructure-based plasmonic FETs (or TeraFETs) suitable for circuit design in the THz range and based on the multi-segment unified charge control model. This model accounts for the electron inertia effect (by incorporating segmented Drude inductances), for the ballistic field effect mobility, which is proportional to the channel length, for parasitic resistances and capacitances and for the leakage current. It is validated by comparison with experimental data and TCAD simulation results. The model can be used for simulation and optimization of sub-THz and THz detectors. Our simulations use up to 200 segments in the device channel. The results are also in good qualitative agreement with the hydrodynamic simulations. Applications of our model could dramatically reduce astronomical design costs of nanoscale VLSI reaching US$1.5 billion for the 3 nm technological node.

Design and analysis of gate all around stacked nanosheet-DRAM for future technology node

This paper reports a stacked Dynamic random-access transistor (DRAM) memory structure that is based on gate all-around nanosheet access transistor. A TCAD study is done to compare nanosheet DRAM and conventional saddle fin recessed channel access transistor (SRCAT) in terms of DRAM electrical characteristics and its row hammer-induced leakage. The nanosheet DRAM shows superior characteristics in terms of current driving capability, speed, and refresh than SRCAT. The nanosheet DRAM also shows significantly lower hammer-induced failure as compared to SRCAT because the original leakage path from the cell to the neighboring cell gets blocked due to the nanosheet device structure. We also investigate the effect of spacer length on nanosheet DRAM characteristics and show that extended spacer length is favorable for having better DRAM characteristics due to the floating body effect. Our study demonstrates the potential, and advantages of nanosheet DRAM architecture compared to the conventional SRCAT DRAM.

A 0.11pJ/bit read energy embedded NanoBridge non-volatile memory and its integration in a 28 nm 32 bit RISC-V microcontroller units

A 28 nm 512 Kb NanoBridge (NB) non-volatile memory is developed for an energy-efficient microcontroller unit. 0.11 pJ/bit read energy is achieved by utilizing an inverter sense scheme thanks to large ON/OFF conductance ratio of a split-electrode NB. The read energy is 71% and 54% less than those of a ReRAM and a silicon oxide nitride oxide silicon commercial embedded NOR flash at the same technology node, respectively. Moreover, a 28 nm 32 bit RISC-V microcontroller unit embedded with a 2 Mb NB non-voltage memory is fabricated and achieves 80 MHz operation frequency.

A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly in mission-critical hardware. At scaled technology nodes, devices are vulnerable to transient or soft errors, such as Single Event Upset (SEU) and Single Event Latch-up (SEL). External radiation, internal electromagnetic interference (EMI), or noise are the primary sources of these errors, which can compromise the circuit functionality. In response to these challenges, the Quasi-Delay-Insensitive (QDI) Null Convention Logic (NCL) asynchronous design paradigm has emerged as a promising alternative, offering advantages such as ultra-low power performance, reduced noise and EMI, and resilience to process, voltage, and temperature variations. Moreover, its unique architecture and insensitivity to timing variations offers a degree of resistance against transient errors; however, it is not entirely resilient. Several resiliency schemes are available to detect and mitigate soft errors in QDI circuits, with approaches based on redundancy proving to be the most effective in ensuring complete resilience across all major QDI implementation paradigms, including NCL, Pre-charge/Weak-charge Half Buffers (PCHB/WCHB), and Sleep Convention Logic (SCL). This research focuses on one such redundancy-based resiliency scheme for QDI NCL circuits, known as the dual-modular redundancy-based NCL (DMR-NCL) architecture, and addresses the absence of formal methods for the verification and analysis of such circuits. A novel methodology has been proposed for formally verifying the correctness of DMR-NCL circuits synthesized from their synchronous counterparts, covering both safety (functional correctness) and liveness (the absence of deadlock). In addition, this research introduces a formal framework for the vulnerability analysis of DMR-NCL circuits against SEU/SEL. To demonstrate the framework’s efficacy and scalability, a prototype computer-aided support tool has been developed, which verifies and analyzes multiple DMR-NCL benchmark circuits of varying sizes and complexities.

New structure transistors for advanced technology node CMOS ICs.

Over recent decades, advancements in complementary metal-oxide-semiconductor integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to three-dimensional (3D) channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore's law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g.in complementary FETs (CFET), 3D stack (3DS) FETs and vertical-channel transistors (VFET), for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

Two-dimensional semiconductor transistors and integrated circuits for advanced technology nodes.

This Perspective aims to provide a concise survey of current progress and outlook future directions in high-performance transistors and integrated circuits (ICs) based on 2D semiconductors.

Design of an SRAM-bitcell with enhanced self-recoverability from soft errors for space and critical terrestrial applications

SSoft errors like single event upset (SEU) and single event double node upset (SEDNU) are significant issues with SRAM-based memory used not only under high radiation environments but also for modern lower technology nodes. The reduction in modern technology may give a higher charge-sharing effect among nodes. The charge-sharing effect means the disturbance on one node may affect the other neighboring nodes. There are many SRAM cells that have been proposed that give single node upset resilience, but very few can solve the charge sharing effect issue or SEDNU. In this paper, a 14T radiation-hardened-based SRAM cell has been proposed to overcome single node upset at any nodes and SEDNU upset at its storage nodes. Simulation results show that only DNUSRM and proposed SRAM give 0% probability of logical flipping. So, out of all compared SRAM cells only DNUSRM and the proposed cell are SEDNU tolerant. The proposed cell gives 50.6%, 22.5%, 0.74%, 17.91%, 60.0%, -19.1%, -5.46%, 25.7%, and 5.22% better total power, area, read speed, write speed, sensitive area, critical charge, hold stability, read stability, and write stability compared to DNUSRM cell. Hence, the better balance among the parameters makes the proposed SRAM more suitable for space and critical terrestrial applications.

Design of low power low area SRAM cell at 180 nm, 90 nm and 45 nm technology nodes

Design of low power low area SRAM cell at 180 nm, 90 nm and 45 nm technology nodes

Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs

Gate-all-around (GAA) nanosheet field-effect transistors (NSFETs) are hailed as the most promising architecture for the incessant scaling of MOSFETs to the sub-5-nm technology node and beyond. Although the GAA structure and the ultra-thin channel lead to a significantly improved static performance owing to the enhanced electrostatic integrity and higher immunity against the short-channel effects, the vertical stacking and the inherent 3-D-geometry result in a large parasitic capacitance and may degrade the dynamic performance. Therefore, it becomes imperative to analyze the parasitic capacitance components in GAA NSFETs and provide design guidelines for optimizing the dynamic performance. To this end, in this work, we have formulated an analytical model for the total gate parasitic capacitance in GAA NSFETs, considering contributions from different parasitic capacitance components. Furthermore, we have also investigated the variation in parasitic capacitance components with the structural parameters for design optimization of GAA NSFETs from a dynamic performance perspective. The result of the developed model is in good agreement with TCAD simulation result indicating the efficacy of the analytical model.

PERFORMANCE COMPARISON OF FINFET-BASED ENERGY RECOVERY ADDER CIRCUITS

The growing demand for secure devices (such as radio frequency identification tags, wireless sensor networks, and smart cards) and the widespread use of the Internet of Things (IoT) have necessitated the secure and energy-efficient design of IoT devices. To date, most of the previous investigations carried out regarding secure devices have focused on the implementation of adiabatic logic circuits for ultra-low power applications. However, to investigate various applications of adiabatic logic circuits, it is essential to analyze their performance characteristics. In this work, the performance of fin field-effect transistor (FinFET)-based adiabatic logic styles using the 4-bit Brent-Kung adder as a reference was evaluated and compared. The simulations performed using Berkeley short-channel insulated-gate common multi-gate FinFET models at 45 nm technology node indicated significant differences in energy consumption, area occupied, peak current pulses, operating frequencies, and temperature effects with respect to the various logic styles studied.

Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs

Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs

Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes

Performance Improvement of Spacer-Engineered N-Type Tree Shaped NSFET Toward Advanced Technology Nodes

SystemC framework for architecture modelling of electronic systems in future particle detectors

The prototyping cost in advanced technology nodes and the complexity of future detectors require the adoption of a system design approach common in the industry: design space exploration through high-level architectural studies to achieve clear and optimized specifications.This contribution proposes a configurable SystemC framework to simulate the readout chain from the front-end chips to the detector back-end. The model is transaction accurate, includes an event generator, interfaces with real physics events, and provides metrics such as readout efficiency, latency, and average queue occupancy.This contribution details the structure of the framework and describes a case study based on the LHCb VeLo upgrade II.

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Novel Slumped SRAM Configuration using QCA Leveraging Differential Voltage Sensing for Enhanced Stability and Efficiency

This paper presents a novel Slumped Static Random-Access Memory (SRAM) configuration utilizing Quantum-dot Cellular Automata (QCA) technology, aimed at achieving enhanced stability and efficiency. Traditional CMOS-based SRAM designs face significant challenges related to power consumption and scalability as technology nodes shrink. QCA, with its potential for ultra-low power dissipation and high-density integration, emerges as a promising alternative. Our proposed SRAM configuration leverages a unique differential voltage sensing mechanism to bolster the stability of the memory cells, particularly under conditions of variability and noise. Through detailed simulations and comparative analysis, we demonstrate that the Slumped SRAM configuration not only improves static noise margin (SNM) but also reduces power consumption and enhances overall readwrite speed. The results indicate a substantial improvement in stability and operational efficiency, positioning this design as a viable solution for future high-performance, low-power memory applications. Through detailed simulations and comparative analysis, we demonstrate that the Slumped SRAM configuration achieves a static noise margin (SNM) improvement of 35% over conventional CMOS-based SRAM designs. Additionally, the proposed design reduces power consumption by 40% and enhances readwrite speed by 25%. These results indicate a substantial improvement in stability and operational efficiency, positioning this design as a viable solution for future high-performance, low-power memory applications.

A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation

A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation