Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs

Abstract

Gate-all-around (GAA) nanosheet field-effect transistors (NSFETs) are hailed as the most promising architecture for the incessant scaling of MOSFETs to the sub-5-nm technology node and beyond. Although the GAA structure and the ultra-thin channel lead to a significantly improved static performance owing to the enhanced electrostatic integrity and higher immunity against the short-channel effects, the vertical stacking and the inherent 3-D-geometry result in a large parasitic capacitance and may degrade the dynamic performance. Therefore, it becomes imperative to analyze the parasitic capacitance components in GAA NSFETs and provide design guidelines for optimizing the dynamic performance. To this end, in this work, we have formulated an analytical model for the total gate parasitic capacitance in GAA NSFETs, considering contributions from different parasitic capacitance components. Furthermore, we have also investigated the variation in parasitic capacitance components with the structural parameters for design optimization of GAA NSFETs from a dynamic performance perspective. The result of the developed model is in good agreement with TCAD simulation result indicating the efficacy of the analytical model.