Data-cell-variation-tolerant triple sampling non-destructive self-reference sensing scheme of STT-MRAM

Abstract

Inevitable process variations (PVT) brought by both the magnetic tunneling junction (MTJ) and MOSFET based on the complementary metal-oxide semiconductor (CMOS) technology become a major obstacle for the mass production of spin transfer torque magnetic random access memory (STT-MRAM). The detriment of the process variations leads to a serious degradation in the fundamental yield with the shrinkage of the technology nodes. However, the conventional data-cell-variation-tolerant (DCVT) sense scheme cannot get the target read yield due to the limited sense margin (SM). To resolve this problem, a DCVT triple sampling non-destructive self-reference sensing scheme (TSNS) is proposed in the paper, which doubles the SM, with lower power consumption and better SM compared with the conventional DCVT sense scheme. Monte Carlo simulation with industry-compatible 65-nm model parameters results show that the proposed sensing scheme shows over 2.5 times higher SM and less power consumption compared to the previous self-reference circuit. The proposed sensing scheme can get the target read yield with lower power consumption.