Abstract
This paper proposes a novel voltage sensing scheme in order to improve reliability and reduce read delay for spin transfer torque magnetic random access memory (STT-MRAM). This scheme utilizes two reference voltages to form a voltage difference from read voltage. The states of magnetic tunnel junction (MTJ) cells are then accurately read by three-input voltage sense amplifier. Simulation results using 28nm Complementary Metal Oxide Semiconductor (CMOS) technology show that read access time can be reduced to 0.7ns with 100mV voltage difference at 1V supply voltage. Read access time is reduced by 83.5% and 53.3% compared with time-based sensing (TBS) scheme and strong positive feedback (SPF) scheme. In addition, high reliability can be achieved because sensing margin increases with discharge of bit lines in a certain time.
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