Implementation of Background Calibration for Redundant FLASH ADC

Abstract

Flash converters are suitable analog-to-digital converter architectures for high-speed applications. However, the benefits in terms of the frequency of smaller technology nodes are hampered by variability, which necessitates the use of large transistors. Comparator redundancy was introduced to overcome this trade-off; the best comparators were selected upfront (either at start-up or in the factory), and the unused comparators could be switched off. This work studies the possibility of performing comparator selection in the background concurrently with normal conversion to increase the converter lifetime. Thus, the system can automatically recover its performance from drifts or failures due to aging, temperature, etc. This paper proposes an embedded solution that includes a calibration stimulus generator (which only requires some external passive elements) and develops system design requirements. In addition, mathematical equations and error sensitivities of the system elements were derived. A 6b flash converter is implemented in UMC180nm technology, and transistor-level simulations of the system are provided to demonstrate the feasibility of the proposed system.