Evaluation of dual-ONOFIC method for subthreshold leakage reduction in domino circuit

Abstract

ABSTRACT A novel dual ON/OFF logic (ONOFIC) pull-down method is presented to reduce subthreshold leakage current in FinFET domino circuit wide OR gates at the 32 nm technology node. An ONOFIC block is inserted in the pull-down network of dynamic and inverted blocks. The HSPICE simulator with the 32 nm BISM4 model is used for the simulation of the proposed work. The outcome of the CLIL (clock is low and inputs are low) state is most effective in reducing the subthreshold leakage current at low and high temperatures. The OR2, OR4, OR8, and OR16 circuits using the proposed method cut down the subthreshold leakage power dissipation up to 48.1% for low power (LP) mode when compared to the LECTOR domino gates in CHIL (clock is high and inputs are low) state, which also reduced subthreshold leakage power dissipation up to 74% for short gate (SG) mode. Due to a lower subthreshold current when all inputs are low at low and high temperatures, the proposed dual-ONOFIC pull-down technique outperforms the ONOFIC pull-up technique in LP mode. When inputs are high at low and high temperatures, the ONOFIC pull-up technique performs better than the dual-ONOFIC pull-down technique.