FDSTDL: Low‐power technique for FinFET domino circuits

Abstract

SummaryMajor issues in designing low‐power high‐speed VLSI circuits are propagation delay, power consumption, and noise tolerance. This paper describes fin field‐effect transistor (FinFET) technology for the design of low‐power VLSI circuits. FinFET uses two gates (front and back) in place of a single gate as in complementary metal‐oxide–semiconductor (CMOS) technology for better control of the channel. A new technique foot driven stack transistor domino logic (FDSTDL) is proposed for designing domino logic circuits in order to reduce leakage power and propagation delay. In this paper, 2‐, 4‐, 8‐, and 16‐input domino OR gates are designed and simulated using existing and proposed techniques in CMOS and FinFET technology. Simulation is done on the 32 nm predictive technology model (PTM) node using HSPICE on a direct current (DC) supply voltage of 0.9 V. The proposed circuit is simulated in two modes of FinFET, short gate (SG) mode, and low power (LP) mode. The proposed technique shows maximum power reduction of 43.45% in SG mode in comparison with conditional stacked keeper domino logic (CSK‐DL) technique and maximum delay reduction of 38.66% in LP mode in comparison with coarse‐mesh finite difference (CMFD) technique at a frequency of 200 MHz.