SCDNDTDL: a technique for designing low-power domino circuits in FinFET technology

Abstract

A new technique called series-connected dynamic node-driven transistor domino logic (SCDNDTDL) is proposed for the design of circuits with high speed and low power consumption in fin-shaped field-effect transistor (FinFET) technology. HSPICE is used to simulate 2-, 4-, 8-, and 16-input domino OR gates in complementary metal–oxide–semiconductor (CMOS) and FinFET technology using the 32-nm Predictive Technology Model (PTM) library with a supply voltage of 0.9 V. The proposed technique shows a maximum power reduction of 73.16% in the FinFET short gate (SG) mode as compared with the conditional stacked keeper domino logic (CSK-DL) technique and a maximum delay reduction of 36.36% in the FinFET SG mode as compared with the voltage comparison-based domino (VCD) technique at a frequency of 50 MHz. The unity noise gain of the proposed circuit is 1.64 to 3.77 times higher in the FinFET SG mode and 1.39 to 3.77 times higher in the FinFET low-power (LP) mode compared with different existing techniques. The proposed circuit has up to 18.94 times higher figure of merit (FOM) in the SG mode and up to 7.14 times higher FOM in the LP mode compared with existing techniques. The proposed circuit in FinFET technology shows a maximum power reduction of 68.47% as compared with its counterpart in CMOS technology for a 16-input OR gate. The proposed circuit has 6.06 times lower energy–delay product and 4.53 times lower power–delay product compared with its counterpart in CMOS technology for a 16-input OR gate.