An efficient low power method for FinFET domino OR logic circuit

Abstract

Advancement in the metal oxide semiconductor field effect transistor (MOSFET) technology leads to large power dissipation, and propagation delay due to extreme scaling of the transistor. So, very large-scale integration (VLSI) industry requires alternative options to meet the demands of the customers. Fin-shaped field effect transistor (FinFET) is new innovative device to replace the MOSFET technology in ultra-deep submicron (ultra-DSM) regime. FinFET mitigates power dissipation to the large extent as compared to the MOSFET, but still the impact of power dissipation degrades the circuit performance. Leakage reduction techniques are further needed in ultra-DSM regime to reduce the power dissipation. Domino logic is commonly used in large memories, and high-speed processors. In this article, a low power domino logic is proposed using FinFET devices. The proposed method is compared to the existing similar domino logic approaches for the different performance metrics at 7 nm technology node using Cadence's tools. The proposed method effectively reduces the leakage power dissipation, and delay penalty for the different logic circuits. The reliability of the domino OR logic is checked by estimating the temperature, and multiple parallel fins variations. The proposed method has a high noise tolerance capacity in term of unity noise gain (UNG) for the domino OR logic as compared to the existing approaches.