A single ended, single port configuration based 9 T SRAM cell for stability enhancement

Abstract

The growing demand for power efficient devices and high-density memories has pushed researchers to develop low power SRAMs. The main objective for these researches is to reduce power consumption and enhances battery life and scaling of technology node. Consequently, in this paper a 9T SRAM bit cell with enhanced stability and single ended, single port configuration is proposed. The cell is designed and simulated at 180 nm technology node with a voltage supply of 1V. The cell proposed has low power consumption owing to single bitline, higher read stability due to isolated read port, better write margin due to disconnected feedback connection and resistant to soft errors because of half select disturbance free architecture. To assess the performance of the proposed cell its performance is compared against existing 6T, 8T, 9TST, SB 9T, TRD 9T, and NTV 9T bit cells. The HSNM (RSNM) and WM values for the proposed cell are equal to 364 mV and 378 mV respectively. The cell is designed to be half select disturbance free and supports bit interleaving. The reliability of the proposed cell is further analysed for local, global and temperature variation. While, the area footprint for the cell is 24.91 μm2.