Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

Abstract

AbstractStatic random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain. This has also bolstered the need for low‐voltage devices. But reduction in operational voltage for cell is limited by process variation. In this work, a single bit line seven‐transistor (7T) SRAM bit cell is reported. The cell is designed for 32‐nm technology node and is functional at 300 mV. The reported cell maintains a 90‐mV hold and read static noise margins (SNMs), while the write margin is 190 mV. The pulse width needed to successfully write into the cell is 30 ns. The performance of proposed 7T cell is compared against different 6T, 7T, 8T, and 10T SRAM bit cells. The hold and read SNMs for proposed 7T are found to be 58.8%, better than single‐ended 6T cell, while the write ability is improved by 71.4%. The leakage current is observed to have decreased by a factor of 14 for Q = 0 (Q being the data storage node) and by factor of 28 for Q = 1, compared to 6T cell. Also, the area footprint of the proposed 7T SRAM cell is 0.442 μm2.