A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell

Abstract

Improving the Noise margin is one of the important challenge in every state of the art SRAM design. Due to the Process variations like threshold voltage variations, supply voltage variations etc.. in scaled technologies, stable operation of the bit cell is critical to obtain with high yield in low-voltage SRAM. In this paper a new assist technique (Read assist and write assist) is proposed to enhance the read and write margins of the 6T SRAM bit cell and the same write assist circuit is applicable to enhance the write margin of the 8T SRAM bit cell. The simulations are performed in 90nm TSMC process Technology node and the read and write margin simulation results are compared with different SRAM circuits like 6T SRAM bit cell with cell ratio of 1, 2, 3 and Dynamic word line swing technique and 8T SRAM bit cell. The effect of temperature and threshold voltage values on Read and Write margins are observed. By using the proposed read assist technique the read margin is improved by 2.375 times for 6T cell and with write assist technique the write margin is improved by 1.89 times for 6T and 8T cells.