Abstract

As silicon technology nodes advance and wafer costs increase, there is a strong incentive to shrink die size and concurrently, die pad pitch. This increased density typically drives higher cost advanced substrates with finer lines and spaces and potentially more layers. As a result of recent constraints on the substrate supply chain, this creates serious availability and cost concerns. A compelling solution is to use fan-out on substrate technology to increase the effective die pad pitch, allowing the use of simpler, lower layer count substrates. ASE used this single die Fan Out Chip on Substrate (FOCoS) approach in engineering and qualification builds starting in 2017 with a traditional fan-out solution. However, with increasing interconnect density, the conventional approach is limited in its ability to work with small bond pad pitches as the die shift during molding creates challenges for manufacturing. An oversized capture pad is often utilized to accommodate this shift and in one prominent case, an additional Cu layer is required. M-series’ use of Adaptive Patterning eliminates the need for oversized capture pads through a unique design-during-manufacturing process which precisely aligns the package interconnect layers to the actual location of each die after molding. This paper will examine the design and manufacturing of a FOCoS package using 4nm silicon through the cooperation of Deca and ASE. The design fans out the interface of a 12mm x 12mm die with 6,000 IO using a single RDL layer and 5 µm line and space. The die has a core pitch of 150µm with an average periphery pitch of 90µm. The resultant M-series flip-chip bumps have a core pitch of 150µm over 75% of the die area with a secondary pitch of 212µm encompassing the remaining perimeter of the die and the 30% body size growth provided by the fan-out region. The relaxed pitch provided by M-series fan-out opens the possibility to use the most cost-effective, readily available type of laminate substrate.

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