Harnessing the power of 4nm silicon with Gen 2 M-Series™ Fan-out and Adaptive Patterning® providing ultra-high-density 20μm device bond pad pitch

Abstract

With the continuing transistor size scaling of advanced silicon, device interconnect bond pads can easily become the limiting factor at 4nm driving an increase in die size merely to fit all the interconnects. At the same time, chiplet-based architectures are moving to higher bandwidth interfaces where designers favor multiple parallel interconnects over classic SERDES connections. This combination of smaller devices and the desire for thousands of chiplet-to-chiplet connections are driving an unprecedented need for shrinking device bond pad pitch.A major barrier in shrinking pad pitch is die shift. Die shift is the natural variation in die location within an embedded structure stemming from chip attach, molding, moisture content, and other process variables. Chips-first fan-out technologies using conventional design methods and mask-based lithography run into barriers in the range of 40 μm to 55μm due to the need for large capture pads to compensate for unavoidable levels of die shift. The industry’s most advanced Cu pillar flip chip on laminate density falls far short of the density need at 4nm with industry experts agreeing on the inability to scale to pitches finer than 35μm.Deca’s M-Series overcomes the pitch barrier using Adaptive Patterning with its unique design-during-manufacturing methods and mask-less laser direct imaging photolithography utilizing 405nm digital patterns. The second-generation M-Series with Adaptive Patterning, or Gen 2, opens up an unprecedented 20μm area array pitch bond pads as a starting point with a roadmap to produce 10μm bond pad pitch within three years.A specific example utilizing 4nm silicon will be presented, demonstrating the flexibility offered by the M-Series’ capability of up to 2,500 IOs per square mm of die size. Two different interface options will be covered in this example. In the first option the pitch will be fanned out to 120μm (the current smallest allowable pitch for a flip-chip on laminate substrate). In the second, the same die will be fanned out to a 90μm pitch M-series interposer containing an embedded die. This M-series interposer will further fan out to a 120μm for mounting onto a substrate. These ultra-high-density interfaces utilize Gen 2’s ability for fan-out with 2um, or larger, RDL traces assuring the smallest possible 4nm die size enabling an appropriate interface pitch for the end user application.