Substrate Warpage Research Articles

Effects of curing condition and solder mask on substrate warpage: an experimental and simulation study

Effects of curing condition and solder mask on substrate warpage: an experimental and simulation study

Recent Progress of TGV Technology for High Performance Semiconductor Packaging

In recent semiconductor packaging, the adoption of through silicon via (TSV) technology has become crucial for the integration of 2.5 and 3D Si chips, and interposers. The TSV offers significant advantages including high interconnect density, shortened signal pathways, and improved electrical performance. However, challenges such as electrical loss, substrate warpage, and high manufacturing costs are associated with TSV implementation. In contrast, glass-based through-glass vias (TGVs) exhibit promising characteristics such as excellent insulation properties, cost-effectiveness, and variable coefficient of thermal expansion (CTE) values that mitigate warpage in stacked devices. Moreover, they facilitate miniaturization and support high-frequency applications. This paper provides an overview of recent advancements in glass substrate, TGV drilling techniques, functional layer depositions, and Cu-filling processes in semiconductor packaging evolution.

Plasma Anneal As a Stress Control Method in Low Temperature Al2O3 ALD Coatings

The control of mechanical physical stress is an important requirement in a variety of applications, such as flexible electronics or thick optical coatings where film stress can cause delamination. Traditionally, in thermal ALD it has been difficult to control the stress. Al2O3 deposited at low temperature is consistently found to have a tensile stress level in the range of a 300 to 450 MPa ( refs 1-3). It is well established that In magnetron sputtering , film stress can be controlled straightforwardly using the Argon pressure during deposition, as this affects the level of bombardment of the growing film with energetic particles.Paranjpe et al ( ref 1) have demonstrated that the use of a plasma anneal leads to densification and transition of the stress from tensile to compressive. The process consists of a sequence of deposition of a thin layer ( e.g. 5 nm) by thermal ALD, followed by exposure to a low energy plasma. The atomic displacements caused by low energy ions from the plasma tend to lead to filling of nanoscopic voids and point defects, thus releasing tensile stress.In this presentation, we will review an in depth study of the effect of various process parameters on the ability of a capacitively coupled in-situ plasma anneal to control stress. The following parameters will be reviewed: Gas composition: Argon plasmas, Oxygen plasmas and Argon oxygen mixtures are compared. Gas Pressure: The effect of gas pressure on plasma characteristics and the resulting modification of the coating is studied RF Power: RF Power was varied between 0 and 300 W ( 1.32 W/cm2) Plasma duration : The duration of the plasma treatment was varied from 0 to 60 seconds.A process window was identified where the plasma anneal can be used as an effective, controllable tool to reduce stress in the coatings. This is illustrated in fig. 1, which shows the substrate warpage (“bow”) observed in 75 mm thick PET foils with a 50 nm Al2O3 coating deposited at 90 °C. It can be seen that the untreated coating (0 sec plasma) has a bow corresponding to a tensile stress of 370 MPa, in accordance with literature values. As the plasma anneal time increases, the stress value decreases. Applying a 60 sec plasma every 5 nm allows to deposit a virtually stress free coating. Simultaneously with the stress reduction, an increase of the optical index and a slight reduction of the thickness are observed, consistent with a densification of the coating.

Copper Content Optimization for Asymmetric Package Substrate Warpage by Genetic Algorithm

Copper Content Optimization for Asymmetric Package Substrate Warpage by Genetic Algorithm

Finite element modeling and analysis method for predicting and optimizing the warpage of construction before flip chip bonding in System-on-Wafer process flow

As one of the solutions to surpass the limitations of Moore's Law in the post-Moore era, System-on-Wafer (SoW) technology provides the capability to integrate multiple chip components onto a single silicon wafer. A new high-density integrated SoW solution is discussed in this article. However, significant warpage can result from mismatches in the coefficients of thermal expansion (CTE) of different materials in a 12-in. wafer, presenting considerable challenges for the flip chip (FC) bonding, installation of power delivery and heat dissipation systems. Severe warpage can directly lead to the failure of the entire system. Therefore, pre-assessment and optimization of the warpage are crucial. This paper proposes a multi-scale modeling approach to assess the wafer warpage prior to FC bonding in the SoW fabrication process. To evaluate the accuracy of the modeling approach, a dummy die to thinned wafer and molding (DDTWM) was first designed and fabricated. The sole distinction in fabrication process between DDTWM and SoW is the absence of through silicon via (TSV) and backend of line (BEOL) metal traces. The simulation and experiment for DDTWM achieve a good level of consistency. In addition, following the completion of warpage simulations on the actual SoW structure prior to FC bonding, utilizing the same modeling approach, we proceeded to perform a Response Surface Methodology (RSM) analysis on several crucial parameters that exert influence on warpage. Subsequent to analyzing the results, optimization simulations were executed, underscoring the significant instructive value of RSM analysis in optimizing warpage within the structure prior to FC bonding in the SoW manufacturing process. This work offers an effective solution for predicting and mitigating substrate warpage prior to FC bonding in the SoW fabrication process, contributing to comprehensive warpage control.

Impact of FCBGA substrate stack-up on BLR performance

Board level reliability (BLR) temperature cycling is a metric for FCBGA field performance, where it is imperative to understand process variation holistically covering both substrate and / or assembly manufacturing process and its impact to product margin. This study focuses on technical reasoning a common FCBGA design manufactured with an identical substrate material set (i.e. core, dielectric, solder mask), assembly bill-of-materials (i.e. underfill, lid, etc.) and assembly site demonstrated different cycles to first failure during BLR testing. Although results far exceeded JESD22-A104 condition G requirements, BLR performance based on identical substrate designs (manufactured at different points in time) proved TV1 (test vehicle 1) performed ~2x better than its TV2 (test vehicle 2) counterpart. To elucidate the primary factor of the disparity in BLR performance, supplier feedback as well as a detailed package construction analysis ensued to compare build-up substrate layer thickness dimensions between TV1 and TV2. Discovery demonstrated a slightly larger volume of a specific layer in the build-up stack within TV2 that generated a higher degree of out-of-plane displacement as compared to TV1. Reproducing the cycles to first failure with the superior TV1 device via the TV1a and impact of substrate warpage was investigated as a factor in the BLR findings driving root cause.

Comprehensive Investigation of In-Plane and Out-of-Plane Die Shift in Flexible Fan-Out Wafer-Level Packaging Using Polydimethylsiloxane

Die shift in fan-out wafer-level packaging (FOWLP) is a major roadblock, limiting package scaling and performance. It not only limits the wire pitch but also results in reliability problems and yield loss. In this work, we systematically investigate and predict the in-plane and out-of-plane die shift through numerical and experimental analysis in FlexTrate, which is a flexible hybrid electronics (FHE) platform based on FOWLP for flexible heterogeneous integration. First, the in-plane die shift is studied through simulation of the molding process and the substrate cure shrinkage. The molding process is simulated through a fluid analysis which explores the shear force. In addition, a thermo-mechanical analysis simulates the polydimethylsiloxane (PDMS) curing process followed by handler release. Based on this model, the effect of die size, die spacing, die thickness, and PDMS thickness on die shift are analyzed. The results indicate that smaller die size has a larger impact on die shift compared to the other factors. The predicted die shift is compared with the experimental results to verify the validity. Further, the experimental characterization of out-of-plane die shift is analyzed through the study of substrate warpage and die placement force which reveal the deleterious effect of high temperature processes. Finally, using the developed numerical model, the die placement is optimized for a surface electromyography (sEMG) system. This detailed analysis sheds light on the various factors which influence die shift, and hence is an important step to push the boundaries of current FHE to new limits.

Validation of New Substrate Design for the Improvement of Strip Warpage on LGA Packages

Land grid array or LGA package of semiconductor has been commonly used on our modern technology, from home gadgets up to industrial uses. Improvements to correct product defects and process issues are introduced to have quality products for customer satisfaction. Substrate warpage have been affecting production performance on semiconductor manufacturing. The unacceptable response results to loss of productivity losses and yield detraction. Different process improvements have been experimented to contain the problem, but results are not maintained and found to be not robust. This is where design innovation plays the part. Solder mask opening on the base material of the substrate is considered to have a favorable response after subjecting it to different environment conditions. From fast indexing and machine movement up to high thermal application on oven curing, having a robust solder mask design makes the unit acceptable and with quality. Product design as mentioned takes on another level to address the phenomenon of substrate warpage. This manuscript will be discussing how the solder mask of the substrate is optimized to achieved minimal or zero substrate warpage by performing different experiments on process and the product itself. Statistical analysis has been the basis for the implementation of the newly validated substrate design.

Study on warpage of the AlSiC substrate in reflow soldering process of the IGBT module

Using the pre-warped substrate to pack IGBT modules can increase the contact area between the substrate and the radiator after the reflow soldering. There are many factors affecting the shape of the substrate’s back after soldering, and determining the effect of each factor by experiments would cost significantly. In this paper, a FEA model of the IGBT module’s reflow soldering process is established by ANSYS to predict the back surface of the pre-warped AlSiC substrate after soldering. Initially, in order to improve the accuracy of the FEA model, the material properties of AlSiC were determined at different temperatures. Subsequently, based on the result of DSC, the solder’s phase transition was simulated in the model. The calculated results showed that the proposed FEA model could predict the shape feature of the AlSiC pre-warped substrate’s back surface after the reflow soldering, and the prediction error of substrate’s residual warpage was 46.05%. The model provides a reliable reference for the design of pre-warped substrate in IGBT module, reducing the test cost and shortening the design period substantially.

Study on Effects of Nonlinear Behavior Characteristics of Prepreg Dielectric on Warpage of Substrate under Laminating Process.

To analyze the effects of nonlinear behavior characteristics of prepreg (PPG) among the insulating materials of substrate and the residual stress of laminating process on the warpage of substrate, this study investigated the continuous laminating process using the numerical analysis by finite element method. The analysis results showed that the warpage of the substrate in the laminating process of PPG was very low, but it increased rapidly in the solder resist (SR) laminating process. As the laminating process of PPG continued, the stress inside the substrate increased continuously and it was predicted to decrease in the SR laminating process. These results confirmed that the warpage of the substrate is influenced the most by the SR laminating process, and that the warpage and stress of substrate accumulated in the laminating process of PPG have significant effects on the final warpage.

Warpage Simulation Study by Trace Mapping Method for FCCSP with ETS Substrate

Abstract ETS (Embedded trace substrate) has become as the mainstream substrate for FCCSP since it has fine trace, better trace dimension control and low cost advantages which compared to normal substrate. But it usually encountered more serious warpage issue for bare substrate and complete package which may influence D/B (die bonding) and SMT yield rate due to its coreless characteristic. Especially for ETS substrate with special trace pattern design (ex. larger Copper area), bare substrate may appear peculiar warpage contour and led to serious non-wetting issue at specific location during D/B process. Thus, if it can predict warpage value and contour accurately for bare substrate and package is an important topic. In this paper, a FCCSP package with ETS substrate was chosen to study trace impact. Bare substrate and package warpage simulation models w/ and w/o considering trace pattern by trace mapping method were performed and compared to shadow moiré results. Analysis results showed that simulation w/ considering trace pattern could get more accurate warpage value and more similar warpage contour for bare substrate and package warpage.

Warpage modeling and characterization of intelligent power modules (IPMs)

Abstract Intelligent power modules (IPMs) are widely used in the electric vehicle (and hybrid electric vehicle industry nowadays due to their high power density and ability to integrate multiple components within a single package. However, the reliability of IPMs is severely degraded by the substrate warpage effect produced during the packaging process. This study therefore develops a computational model to analyze the warpage of the IPM assembly at various stages of the packaging process. The validity of the simulation model is confirmed by comparing the numerical results for the warpage of the direct plated copper substrate with the experimental observations. Taguchi experiments are then performed to examine the effects of eight control factors on the IPM package warpage following the post-mold cure (PMC) process, namely (1) the dam bar layout, (2) the epoxy molding compound (EMC) thickness, (3) the lead frame thickness, (4) the ceramic thickness, (5) the bottom layer Cu foil thickness, (6) the top layer Cu foil thickness, (7) the ceramic material type and (8) the EMC material type. Finally, the Taguchi analysis results are used to determine the optimal packaging design that minimizes the warpage of the post-PMC package.

Evaluation of Direct Printed Heat Sinks on Metallized Ceramic Substrate for High-Performance Power Modules

In this article, we propose a new packaging technology enabling the development of a high-performance power module for harsh environments. This approach is based on the use of the selective laser melting (SLM) technique in order to directly print metal heat sinks on the backside of the metallized substrate. In order to explore the viability of this method, the assembled parts were evaluated thoroughly after the manufacturing process. Moreover, their robustness was assessed during aging under harsh conditions. Results show that the ultimate tensile strength and yield strength of the printed alloy are higher than the casted AlSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sub> Mg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> counterpart. The interfaces between the printed alloy and the substrate Al metal layer do not show any weaknesses, and shear stress values are higher than 100 MPa. For all heat sink patterns, the substrate warpage is reduced during thermal cycling due to the Al alloy creeping, while the highly curved substrates show cracks in the ceramic after 400 cycles. Accordingly, direct printing of heat sink with patterns based on fins array reveals a promising path for high-reliability, high-performance power module packaging.

Validation and Optimization of Calculated Stress Fields in Double-Mold Optoelectronics Sensor Packaging

Thermomechanical modeling of a new double-overmolded optical sensor package, comprising a highly filled, as well as an unfilled, strongly thermally expanding transfer molding compound, is presented. Materials’ characterization of the polymers using thermal, thermomechanical, dynamic, and optical correlation methods was used to set up finite element models of the three major steps in the assembly packaging process. The results of the simulation were validated by in-plane stress determination using a piezoresistive integrated circuit measured at various temperatures. In addition, the overall package substrate warpage was optically characterized while loading the sample on a hot plate. Agreement between the measurement and the simulation was only found when the stress-free state of the polymers was set to be at the curing-onset temperature. The results obtained are compared with different levels of complexity on materials’ characterization and constitutive modeling and could finally be used for sensitivity analysis of the sensor package design. A thicker and more compliant transparent molding compound in this package was found to reduce the stresses that could cause delamination.

Distortion and Dilution Behavior for Laser Metal Deposition onto Thin Sheet Metals

The combination of additive manufacturing and incremental sheet forming offers great flexibility in the manufacture of function-integrated parts. In this study, both processes were carried out by the same CNC machine. This offers the possibility to manufacture large-scale lightweight parts with smaller additive parts on it in one machine and clamping device. Additionally, the process combination can lead to a reduced energy and material consumption for small batch sizes. DC01 sheets are used as a substrate with two different initial conditions. The first condition is as delivered steel sheet and the second is an incrementally formed with a thickness of 0.5 mm. The additive manufacturing was conducted by laser metal deposition (LMD). The powder material is a stainless steel 316 L. A segmentation of the cladding surface was applied and the path strategy of the laser movement was varied simultaneously to analyse the warpage of the thin substrate. It is shown that there is a dependency between the build-up strategies and the melt pool temperature, the thermal distortion, the dilution and the size of the cladding area. A segmentation of the working surface causes a lower melt pool temperature and thermal distortion. The lower melt pool temperature also generates a reduced dilution zone.

Self-Annealing Behavior of Electroplated Cu with Different Brightener Concentrations

The self-annealing (room-temperature annealing) behavior of electroplated Cu has recently received a great deal of attention from the microelectronics industry because its remarkable microstructure transition is closely related to several crucial reliability issues, including substrate warpage, pinhole formation, corrosion, and electrical resistivity. Organic additives (e.g., brightener and leveler) in the electrolyte are indispensable for the superfilling of electroplated Cu in blind-/through-hole structures, and their effects on the Cu self-annealing behavior should be quantitatively characterized. We investigated the effect of brightener concentration (Cb) on the crystallographic transition of electroplated Cu (including the evolutions of the grain size, grain boundaries, and grain orientation) by means of X-ray diffraction (XRD), electron backscatter diffraction (EBSD), and high-resolution transmission electron microscopy (HRTEM) during self-annealing. Furthermore, the mechanical properties of electroplated Cu (hardness and Young’s modulus) resulting from different Cb were investigated through nanoindentation testing. The concentration depth profiles of the impurities (Cl, N, C, and S) in the electroplated Cu were characterized by time-of-flight secondary ion mass spectrometry (TOF-SIMS). These investigations showed that Cb is a dominant factor of the Cu self-annealing behavior and mechanical properties, and a sufficient Cb is required for the initiation of a remarkable crystallographic transition even at room temperature.

Warpage of single crystal silicon substrate irradiated with permeable pulse laser

Warpage of single crystal silicon substrate irradiated with permeable pulse laser

Understanding the Effects of Process Parameters to Compensate for Substrate Warpage in Chip on Flex (CoF) Assembly Using Conventional Reflow

Abstract Mounting rigid silicon (Si) die on a flex substrate presents a unique set of challenges. Substrate surface flatness and warpage of the flex substrate before and during thermal processing being two of the biggest issues. Various processes such as thermocompression bonding using anisotropic conductive films and thermosonic bonding using non-conductive adhesives have been shown to be effective for chip on flex (CoF) applications. However, these processes sacrifice process throughput and are less cost effective. Hence these methods may not be suitable for high volume manufacturing (HVM). For this reason, a process that is suitable for HVM and uses standard reflow processes and equipment is highly desirable. This works presents preliminary results for such a CoF process that uses a simple fixture and standard processes, materials and equipment. CoF process for Si die using two types of interconnects, solder balls or Cu pillars, was developed. Solder paste was stencil printed before pick and place of the Si die to offset the lack of flex substrate flatness and substrate warpage. The effect of stencil aperture diameter and placement force on process yield and stand-off height was studied. It was demonstrated that high yield can be obtained with a process that uses wider stencil aperture opening for both type of interconnects investigated. It was also observed that the placement force did not have any effect on process yield or stand-off height. The process can also be easily scaled up for HVM.

Material Characterization and Warpage Modeling for Power Devices Active Metal Brazed Substrates

The metallized insulating substrates work as mechanical supports for the circuitry of Power Module Packages. Due to their specific functions, substrates for power electronics are made by different materials. The conductive metal layers can assume different functions: the top metal serves as power circuitry routing while the bottom metal improves the mechanical robustness and thermal efficiency. Ceramic layer provides excellent electrical insulation. These features play an essential role in the operation of power modules, which are often operated at high voltage and high current density. The substrates, composed by materials with different thermal expansion coefficients, are subjected to cyclic stresses due to temperature variations induced by operative working conditions. The substrate layouts typically include differences in shape and/or thickness between the top and the bottom side; this generates asymmetrical distributions of stress/strain resulting in overall warpage. The variations of this warpage induce mechanical fatigue during lifetime and represent a limiting factor for reliability. The scope of the presented work is the characterization of the out of plane warpage of Active Metal Brazed substrates (AMB) by means of numerical approach. The elastoplastic properties of metal and ceramic have been measured, evaluating the thermal softening of the copper as well. These characteristics are needed to calculate AMB warpage through Finite Element Models (FEM), simulating the warpage induced by a passive temperature cycling. Warpage computed from numerical model have been benchmarked and validated with optical warpage measurements. The validated numerical model has been developed to optimize the substrate warpage variation during cycling improving the whole package reliability.

Development, Implementation, and Characterization of a 64-Element Dual-Polarized Phased-Array Antenna Module for 28-GHz High-Speed Data Communications

Silicon-based millimeter-wave (mm-wave) phased-array technologies are enabling directional wireless data communications at Gb/s speeds. In this paper, we review and discuss the challenges of implementing a multichip phased-array antenna module for mm-wave applications using organic buildup substrate technology. A prototype test vehicle has been fabricated and studied to evaluate the antenna and interconnect performance, dielectric properties, package substrate warpage conditions at different temperatures, chip- and board-level joint process reliability, and thermal management feasibility for cooling. Based on the learning from the test vehicle, an organic-based multilayered phased-array antenna package for 28-GHz mm-wave radio access applications is implemented. The package incorporates 64 dual-polarized antenna elements and features an air cavity common to all antennas. Direct probing measurements on a single-antenna element of the package show over 3 GHz of bandwidth and 3-dBi gain at 28 GHz. A phased-array transceiver module has been developed with the package; the module includes four SiGe BiCMOS ICs attached using flip-chip assembly. Module-level measurements in the TX mode show a 35-dB near-ideal output power increase for 64-element power combining; 64-element radiation pattern measurements are reported with a steering range of ± 50° without tapering in off-boresight directions, and 64-element radiation pattern measurements with tapering show achievement of a sidelobe level lower than −20 dB. The transceiver modules achieved 20.64-Gb/s throughput with 256 QAM and 800-MHz bandwidth in direct over-the-air link measurement results.