Substrate Warpage Research Articles

Integrated Hardware and Software for Improved Flatness Measurement With ATC4.1 Flip-Chip Assembly Case Study

Over the past four decades, microelectronic packaging technology has evolved from peripheral, through-hole, and bulk configurations to area-array, surface-mount, and small-profile ones. Among these approaches, flip-chip attachment has become the most favorable choice for its large input/output capabilities and short signal path distributions. Given the prediction that the chip size and power of a single chip package will increase dramatically, substrate warpage of flip-chip packages during assembly and usage has become a major concern. Warpage could cause misalignment between the chip and the substrate, prevent the solder balls from making contact with the substrate flip-chip pads during the reflow soldering process, and induce crack nucleation at the board underfill interface during long-term usage. In this paper, the authors developed an integrated large-area shadow moire system for measuring small and large board and chip package warpage. The hardware is designed to carry out warpage measurement with a resolution on the order of micrometers. Combined with software, the integrated system is fully automated and highly accurate. For the case study, the system is used to characterize the substrate warpage of flip-chip on organic board assemblies. Warpage of substrates at the initial bare-board stage, post-reflow, and post-underfill is measured at room temperatures. It is found that by properly selecting initially warped substrates, post-reflow and post-underfill warpage can be reduced. In addition, warpage measurements at elevated temperatures during thermal cycling and power cycling show that power cycling poses a smaller impact on substrate warpage.

A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification

This paper presents a theoretical yield model for area array solder interconnect process. To achieve a successful solder joint, contact between the solder ball and its associated wettable pad area is essential because without contact, the solder ball cannot initiate wetting its associated pad and, finally, is found an open defect. When an area array solder joints are made simultaneously, it may happen that some of the solder joints in a chip cannot make contact with their associated pads because of the variations of design parameters such as solder ball size, pad size and height, substrate warpage, etc. The yield model provides the relationships of the interconnect yield to the statistical variations of the design parameters. A series of experiments were performed with specially designed area array flip-chips and substrates to verify the model, focusing on the effects of the solder ball size variation and the number of solder joints on interconnect yield. The experimental observations agree well with the model prediction.

A Study on Warpage of Flexible SS Substrates for Large Area MCM-D Packaging

This paper presents potential application of stainless steel (SS) as a base substrate material for large area multi-chip module-deposited (MCM-D) packaging. Preliminary results on via formation on SS substrates by laser drilling, dielectric coating on SS surface and on via sidewall, via filling for front-to-back interconnects, and subsequent curing of via filling material are reported in this paper. The objective of this DARPA funded MCM-D Consortium is to investigate the feasibility of application of stainless steel materials for large area MCM-D packaging through laboratory prototypes and simulated thin film process. This paper particularly addresses the warpage issues related to via formation, dielectric coating on the substrates, and via filling process after substrates were exposed to temperatures above 130 °C for two hours. The change in process induced warpage was quantified by the simple non-destructive Shadow Moire´ technique. The end objective of this work is to be able to fabricate large area 24 in.×24 in.SS substrates with minimum warpage. The study shows that SS can be a candidate substrate for large area MCM-D packaging. [S1043-7398(00)00702-7]

Effect of Frit Added in Ag-Paste on Warpage of Multilayered Glass-Ceramics Substrate.

The effect of frit added in Ag-paste on warpage of co-firing multilayered glass-ceramics substrate was investigated. BaO-Al2O3-SiO2 system glass was used as the added frit. The difference of shrinkage between Ag paste and the glass-ceramics increased with increasing the frit added in the Ag-paste. But, the warpage of co-firing multilayered substrate reduced with increasing the frit added. From these results, it was found that the warpage in our system was not due to the shrinkage mismatch between the substrate and the inner conductor materials, but it was caused by the change of glass-ceramics sintering behavior according to diffusion of silver, as previously reported by other investigators. Electron probe micro-analysis (EPMA) revealed that the glass layer suffered modifications from the added frit formed around the Ag-inner conductor, and that this layer prevented Ag from diffusing into the glass-ceramics. Therefore, the sintering behavior of the glass-ceramics in the neighborhood of the Ag-inner conductor did not change locally, and the warpage of cofiring substrate reduced with increasing the frit added in Ag-paste.

Nonlinear Analysis of Full-Matrix and Perimeter Plastic Ball Grid Array Solder Joints

The application of Ball Grid Array (BGA) technology in electronic packaging on high I/O plastic and ceramic packages has grown significantly during the past few years. Although PBGA (plastic BGA) has several advantages over fine-pitch Quad Flat Pack (QFP) in terms of smaller package area, higher I/Os, lower switching noise, large pitch, higher assembly yield, and improved robustness in manufacturing process, potential package reliability problems can still occur, e.g., excessive solder joint deformation induced by substrate warpage, moisture ingression (popcorn effect), large variation in solder ball size, voiding as a result of flux entrapment and improper pad/solder mask design (Marrs and Olachea, 1994; Solberg, 1994; Freyman and Petrucci, 1995; Lau, 1995; Donlin, 1996; Lasky et al., 1996; Munroe et al., 1996). Regardless of its improved thermal fatigue performance over the past few years through an extensive amount of research, the BGA solder joint may still pose a reliability issue under harsh environment, e.g., automotive underhood, larger package size, or higher temperature and temperature gradient due to increase in power dissipation of the package. Numerous studies in BGA solder joint deformation and reliability under thermal and mechanical loadings can be found in the literature, e.g., Borgesen et al. (1993), Choi et al. (1993), Guo et al. (1993), Ju et al. (1994), Lau et al. (1994) Lau (1995), and Heinrich et al. (1995). Also, reliability prediction models have been developed by, e.g., Darveaux et al. (1995) and Darveaux (1996). The present study focuses on the application of a detailed nonlinear finite element analysis (FEA) to studying the thermal cyclic response of solder joints in two particular BGA packages, full-matrix and perimeter. Both time-independent plasticity and time-dependent effect, i.e., creep and relaxation, are considered in the constitutive equations of solder joint to evaluate the discrepancy in the results of life prediction. The critical solder joint is identified, and the locations that are most susceptible to fatigue failure in the critical joint are discussed. Some limitations in computation and reliability prediction are also discussed.

Warpage and Interfacial Stress Distribution in a Single-Level Integrated Module (SLIM)

The thermomechanical behavior of a new multilayered substrate with embedded passive components is the focus of this study. Such structures are typically susceptible to localized interfacial stresses near the free edge, which might initiate delamination and subsequent failure of the electronic component. The effect of some key parameters—base layer material, interlayer dielectric material, base layer thickness, and temperature range—on substrate warpage and interfacial shear and peel stress distribution is presented. Material and design recommendations for improved thermomechanical response are suggested based on this initial parametric study.

Experimental Measurement and Analysis of Microelectronics Application Polymer Materials Properties

AbstractA laser based surface scanning technique was utilized to measure the polyimide coated silicon wafer curvature resulting from thermal cycling and mismatch, Meanwhile, mechanical properties of polyimide thin film were characterized by DMA, TMA and tensile test. Based on the obtained material properties, A FEA model was developed to analyze the experimental results -reasonable correlation was obtained.Similar approaches were taken one step further in the MCM silicon substrate curvature measurement. In a MCM package with silicon substrate, epoxy adhesive, and ceramic package, substrate warpage was developed in a thermal cycle due to thermal mismatch between the substrate and the package and coupling effect linked by epoxy adhesive. Three different substrate curvature measurement techniques were applied to identify the substrate curvature and epoxy thin film properties were also well characterized. A 3D FEA model incorporating with the epoxy material properties was developed to analyze the substrate warpage and investigate an optimal package design.