Abstract

As one of the solutions to surpass the limitations of Moore's Law in the post-Moore era, System-on-Wafer (SoW) technology provides the capability to integrate multiple chip components onto a single silicon wafer. A new high-density integrated SoW solution is discussed in this article. However, significant warpage can result from mismatches in the coefficients of thermal expansion (CTE) of different materials in a 12-in. wafer, presenting considerable challenges for the flip chip (FC) bonding, installation of power delivery and heat dissipation systems. Severe warpage can directly lead to the failure of the entire system. Therefore, pre-assessment and optimization of the warpage are crucial. This paper proposes a multi-scale modeling approach to assess the wafer warpage prior to FC bonding in the SoW fabrication process. To evaluate the accuracy of the modeling approach, a dummy die to thinned wafer and molding (DDTWM) was first designed and fabricated. The sole distinction in fabrication process between DDTWM and SoW is the absence of through silicon via (TSV) and backend of line (BEOL) metal traces. The simulation and experiment for DDTWM achieve a good level of consistency. In addition, following the completion of warpage simulations on the actual SoW structure prior to FC bonding, utilizing the same modeling approach, we proceeded to perform a Response Surface Methodology (RSM) analysis on several crucial parameters that exert influence on warpage. Subsequent to analyzing the results, optimization simulations were executed, underscoring the significant instructive value of RSM analysis in optimizing warpage within the structure prior to FC bonding in the SoW manufacturing process. This work offers an effective solution for predicting and mitigating substrate warpage prior to FC bonding in the SoW fabrication process, contributing to comprehensive warpage control.

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