Thermal stress analysis and failure mechanisms for through silicon via array

Abstract

This study presents the thermal stress distribution for through silicon via array. Through silicon via (TSV) is the critical technology for three dimensional integration technology, which provides vertical interconnections between stacking dies. But, there are still some challenges for the 3D IC and TSV technology. One issue is that there are large coefficient of thermal expansion (CTE) differences between silicon substrate, dielectric material, and filled metal in TSV structure. The CTE of copper is six times larger than the CTE of silicon dioxide. Higher CTE mismatch will generate higher thermal stress at the interface of different materials and result in materials failure or delamination. In this paper, we investigated the thermal-mechanical stress distribution of a three dimensional TSV array model under the accelerated thermal cycling loading condition by finite element analysis (FEA). Due to the different thermal expansion of each material in TSV structure, the TSV structure squeezes the surface area between TSVs at high temperature and then result in compressive stress occurs at the surface area between TSV. The stress analysis shows that maximum thermal stress occurs around pads, and which may result in failure or delamination of TSV pads. Besides, we discussed the pad dimension effect to reduce the stress near the pad. According to the simulation result, larger pads TSV array has smaller space between each TSV; therefore, the stress is higher at that middle space surface. Smaller pad size has higher stress near the corner of pads; however, it has smaller stress state at the middle of bottom pad. And simulation also shows that via diameter of copper yield higher stress than die thickness. With these results, this study will help to obtain a clear thermal stress distribution of TSV array and find out possible failure regions in the TSV structure.