Abstract

Silicon interposers with through-silicon vias (TSVs) have been widely explored to connect multiple chips using high-density fine-pitch lateral interconnects. However, there are challenges with the TSVs in silicon interposers: (1) TSV losses increase as TSV height increases and are much higher in low-resistivity silicon substrates, which are more economical, than in high-resistivity silicon substrates, and (2) coefficient of thermal expansion (CTE) mismatch between the copper and silicon leads to stress generation. To address this set of challenges, we fabricated and characterized two novel photodefined TSVs for silicon interposers: polymer-clad TSVs and polymer-embedded vias. The fabricated polymer-clad TSVs consist of a ~20 μm thick photodefined dielectric liner instead of a 1 μm thin SiO2 liner, while the polymer-embedded vias consist of copper vias embedded in photodefined polymer wells within the silicon wafer. Compared to the conventional TSVs with thin (~1 μm) SiO2 liner, ~3.5X and ~20X reductions in TSV insertion loss can be obtained at 25 GHz using the fabricated polymer-clad TSVs and polymer-embedded vias, respectively. Full-wave EM simulations were performed in HFSS to compare the insertion loss of the novel TSVs with the conventional TSVs. With respect to the polymer-clad TSVs, in addition to the reduction in TSV insertion loss, a possible reduction in TSV stresses can be obtained using a low Young's modulus material for the thick liner. Finite-element modeling (FEM) simulations were performed in ANSYS to analyze the possible stress reduction that can be obtained using the fabricated polymer-clad TSVs compared to the conventional TSVs. Finally, four-point resistance measurements were performed for the novel TSVs to prove their high yield. In summary, this presentation will report fabrication and resistance measurements of the novel polymer-clad TSVs and polymer-embedded vias as well as HFSS and ANSYS simulations for the novel TSVs.

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