Warpage Simulation Study by Trace Mapping Method for FCCSP with ETS Substrate

Abstract

Abstract ETS (Embedded trace substrate) has become as the mainstream substrate for FCCSP since it has fine trace, better trace dimension control and low cost advantages which compared to normal substrate. But it usually encountered more serious warpage issue for bare substrate and complete package which may influence D/B (die bonding) and SMT yield rate due to its coreless characteristic. Especially for ETS substrate with special trace pattern design (ex. larger Copper area), bare substrate may appear peculiar warpage contour and led to serious non-wetting issue at specific location during D/B process. Thus, if it can predict warpage value and contour accurately for bare substrate and package is an important topic. In this paper, a FCCSP package with ETS substrate was chosen to study trace impact. Bare substrate and package warpage simulation models w/ and w/o considering trace pattern by trace mapping method were performed and compared to shadow moiré results. Analysis results showed that simulation w/ considering trace pattern could get more accurate warpage value and more similar warpage contour for bare substrate and package warpage.