An embedded trace FCCSP substrate without glass cloth

Abstract

Coreless embedded trace has attracted interest from mobile device, in few metal layer Flip-Chip Chip Scale Package (FCCSP) substrate design, for electrical performance, high density, and thickness reduction. However, the mainstream Prepreg (PP) dielectrics with glass-cloth utilized in coreless embedded trace substrate (ETS) are insufficient to fulfill future requirements of warpage behavior, RF performance, miniaturization and even cost. This research is targeted on developing an alternative 2-layer coreless ETS technology platform, without glass-cloth, to make up the above shortage. The total solution from substrate fabrication to package verification had been studied. With the design for manufacturability and reliability approaches, a pioneering 120μm thin 2-layer coreless ETS, by Ajinomoto Buildup Film-like dielectric without glass-fabric, was developed for FCCSP, with both experimental and simulation efforts. Compared with the conventional PP with glass-cloth, a cost effective substrate featured with 20% thinner and 20% less package warpage deformation was gained. The new material scheme also allows better compatibility with fine pitch design and RF transmission. This technology can be an extended process platform to higher multi-layer (≥3) advanced coreless substrate for flip chip BGA & module assemblies.