Trend plots for compound selection utilized for warpage design of MUF FCCSP with 4L ETS

Abstract

With the integrated circuit (IC) development on extremely advanced photolithographic techniques, the assembly house is in thirsty need of an important change for substrate portion if possible to fall further and further behind continuously. Most substrates are composite structures of epoxy-based fiberglass reinforced dielectric layers that are interleaved with copper foil used for conducting electric current (power and ground planes). These layers are stacked and cured under certain prescribed temperature and pressures during the laminating process. While the technology gap of flip chip (FC) substrate is the addition of layers to purvey continuously as the ultimate demand to provide a device with improved electrical performance, material cost as high as 70% approached cost of total FC package and better electrical integrity as the end users' striving are forcing substrate manufacturers to eliminate core layer as coreless substrate and design unbalanced thickness of top / bottom copper foil. Thermally induced residual stress caused by the coefficient of thermal expansion (CTE) mismatch between different substrate materials, combined with hydrothermal effects, can introduce warpage, especially for low rigidity property of prepreg (PP) and high flexibility structure of ultra-thin embedded trace substrate (ETS). While conventional solution of semi-additive process (SAP) to fine pitch of copper line / space (L/S) caused risk of solder bridging in assembly process of flip chip bonding (FCB) as the circuit go to 45 μm. Although the co-planarity between FC and substrate is necessary to optimize for joint solder bump by surface mount technology (SMT), the flexibility for ultra-thin die and ETS maybe is another root cause to improve for joint copper pillar bump by thermo-compression bonding (TCB). Thus, the product of ETS with asymmetric structure of top / bottom copper foil and solder mask has developed in past few years for cost effect and electrical performance. Furthermore, while the two key industry trends that the drive towards finer-pitch ( eff (T) (effective CTE(T)) depended on temperature-dependent path of modulus (E(T)) from T ref (Reference temperature) to T uni (Uniform temperature) is non-incremental solution based on stress conservation law. Stress conservation law is particularly well suited for warpage prediction because of its simple and further derived in non-incremental solution, and then construction of trend plot for selection of compound type at 25°C and 260°C can be performed in 2-dimentional diagram by axes of CTEeff and E. Finally, with the warpage optimization through this visual 2D plot and warpage design on compound type validated with measurement, companies are experiencing improvements and having a direct impact to follow specification of solder bond co-planarity.