Various Chip Attach Evaluations in a Fine Bump Pitch and Substrate Flip Chip Package

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Emerging markets are always driving demand for higher performance, higher bandwidth, lower power consumption as well as increasing functionality in mobile applications. Packaging technology has become more challenging and complicated than ever before, driving advanced silicon (Si) nodes, finer bump pitch as well as finer line width and spacing (LW/LS) substrate manufacturing capabilities to satisfy the increasing requirements in the semiconductor industry. As increasing input/output (I/O) counts in a package are needed in mobile devices, packaging solutions are migrating from traditional wire bond packages to flip chip interconnect to meet these requirements. Flip chip chip scale package (fcCSP) is viewed as an attractive solution for complicated and highly integrated systems with multiple functions and heterogeneous mobile applications. Although emerging markets are driving advanced technologies in high performance mobile devices, assembly cost is still the major issue to be addressed. In addition, due to the fast growth in emerging markets for mobile applications, advanced Si node technology development for mobile applications is moving to 10nm technology (and below) and pursuing the die size reduction, efficiency enhancement and lower power consumption now. For the sake of realizing the 10nm extremely low-k (ELK) performance in a flip chip package, this paper address the technology of Mediatek innovation package (MIP) design by using copper (Cu) pillar bond-on-lead (BOL) with embedded trace substrate (ETS) to achieve low cost, finer bump pitch as finer LW/LS requirements. The 10nm chip-package interaction (CPI) study in a 15×15mm fcCSP with finer Cu pillar bump pitch of 60μm and a 2-layer ETS with finer LW/LS design is illustrated. The utilizations of 60μm bump pitch with escaped trace and mass reflow (MR), thermo-compression bonding (TCB), TCB with non-conductive paste (TCNCP), and laser assist bonding (LAB) flip chip attach process are estimated. The quick temperature cycling (QTC) test with temperature range of -40°C to 60°C is performed to realize the ELK performance in this 10nm flip chip package. Moreover, the comparison of different under bump metallization (UBM) sizes, existence of polyimide (PI) layer and reflow profiles has been also studied. With the evaluated results, not only the significant factors that impact ELK performance can be obtained, but the optimized reflow profile can also be established to enhance the yield in flip chip attach processes. It is believed that the illustrated robust flip chip attach processes examined in this paper can guarantee 10nm fine bump pitch flip chip assembly yield with less ELK damage risk in the future.