7nm Chip-Package Interaction Study on a Fine Pitch Flip Chip Package with Laser Assisted Bonding and Mass Reflow Technology

Abstract

With the fast growth in emerging technologies for mobile applications, packaging solutions are being driven by advanced Silicon (Si) nodes technology (down to 7nm), smaller form factor package designs, efficiency enhancement and lower power consumption. The flip chip chip scale package (fcCSP) has been widely adopted as the solution for mobile devices to satisfy these challenging requirements. In order to create a lower cost solution, the fcCSP uses the cost-effective combination of copper (Cu) pillar bumps, embedded trace substrate (ETS) technology, mass reflow (MR) chip attach and molded underfill (MUF) processes. Although the utilization of MR chip attach is a cost-effective process for flip chip package assembly, there is a high risk for a bump to trace short, especially for the designs with finer bump pitch and line width / line spacing (LW/LS) with an escaped trace. To reduce this risk, the laser assisted bonding (LAB) methodology is introduced to study the 7nm chip-package interaction (CPI) of an fcCSP with a 60μm bump pitch and escaped traces design in this paper. For the purpose of measuring the extremely low-k (ELK) performance in a 14x14mm fine pitch fcCSP with 7nm live die, the thunder test (two-times MR and quick temperature cycling (QTC) tests) as well as the hammer test with multi-reflow process (peak temperature at 260 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sup> C) have been evaluated after performing LAB and MR chip attach methodologies. The results show that although both chip attach methodologies can pass the normal requirements of the thunder and hammer tests, the utilization of LAB technology can further enhance the strength of ELK and produce better yield performance. From these results, it is believed that LAB not only can guarantee assembly yield with less ELK damage risk in the examined 7nm fcCSP, but can also accommodate Si node and bump pitch reduction with a finer LW/LS substrate with escaped traces design.