Development of thin flip chip package with low cost substrate technology

Abstract

Emerging markets are always driving demand for higher performance, higher bandwidth, lower power consumption as well as increasing functionality in mobile applications. Packaging technology has become more challenging and complicated than ever before, driving advance Silicon (Si) nodes, finer bump pitch as well as finer line width and spacing substrate manufacturing capabilities to satisfy the increasing requirements in semiconductor industry. As increasing input/output (I/O) counts in a package are needed in mobile devices, packaging solutions are migrating from traditional wire bond packages to flip chip interconnect to meet these requirements. Flip chip chip scale package (fcCSP) is viewed as an attractive solution for complicated and highly integrated systems with multiple functions and heterogeneous mobile applications. Although emerging markets are driving advanced technologies in high performance mobile devices, assembly cost is still the major issue to be addressed. As the substrate cost is always the significant factor in a flip chip package, flip chip assembly with a low cost substrate has become a hot topic in the industry. The flip chip interconnect with copper column bond-on-lead (BOL) structure on embedded trace substrate (ETS) and molded interconnect substrate (MIS) has been widely adopted for low cost demand. In addition, flip chip interconnect with copper column bond-on-lead (BOL) and enhanced processes (fcCuBE®) can also help to deliver a high performance packaging solution with a cost effective mass reflow (MR) manufacturing process. In order to develop the low cost flip chip packages, flip chip packages with fcCuBE®, low cost substrate and thin package profile technology is evaluated. The warpage/coplanarity behaviors and long term package reliability data with different substrate format, such as four-layer cored substrate and coreless ETS, three and two layer coreless ETS with different prepreg thickness as well as two layer MIS in a flip chip package will also be addressed. Through these results, it not only illustrates the robust flip chip bump process with copper column technology in fcCuBE® which can be adopted with low cost substrates but it also can achieve bump pitch reduction, performance improvement and Si node reduction. It is believed that this successful data can show how a flip chip package is an enabling technology for highly integrated, miniaturized, low profile and cost-effective packaging solutions.