A design-of-experiment (DOE) to optimize a SiP design for connectivity applications

Abstract

System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever smaller products is continuously pushing development of new materials, components and assembly technologies. An optimization study of a SiP design based on a functional product is discussed in this presentation to address the following: 1. Design optimization to reduce component spacing with varied assembly challenges 2. Substrate stack-up optimization for z-height reduction with coreless substrate technologies 3. Flip chip (FC) bump pad optimization for ball bumped or copper-pillar bumped CMOS silicon's 4. Cost reduction potential to replace SOP with paste printing using u-stencil for flip chip applications 5. Assessment of different MUF and fluxing underfill (FU) materials To accomplish these objectives, two types of bumped silicon wafers/dice, three different substrates and four different materials were implemented in this DOE. Short-looped wafers of an actual live device were bumped with CuP pillar as well as with SnAg ball bumping technologies. All three substrate designs are coreless, as compared with the original POR conventional design. One substrate was designed with the plan-of-record (POR) component spacing on a 6-layer stack-up that results in ∼ 290 um overall z-height; X-Y-Z size reductions were achieved on the alternative 4-layer design that has reduced component spacing as well as a reduced overall z-height of ∼ 190 um; furthermore, embedded trace substrate (ETS) was used as the top layer for the 4-layer designs to ensure improved routing capabilities. Subtle differentiation between these two 4-layer designs is in the die shadow area on the top ETS layer: while one design uses solder mask defined pads (SMD) the other uses the ETS dielectric materials to define the flip chip bonding pads without solder mask (NSMD). The latter design facilitates the MUF flows for ultralow stand-off flip chip solder joints and make it a likely “universal” pad design for both CuP and SnAg flip chip bump attach. Four different MUF materials along with one FU materials were used for DOE assembly: the first MUF is the POR material currently used in HVM production with nominal filler sizes; 2nd MUF is for low warpage applications (especially for thin, coreless substrate); 3rd MUF has a smaller filler size that is optimized for small stand-off flip chip bumps and the last MUF has a much improved thermal conductivity and is assessed here for its fit-for-use in other high thermal density applications. FU used is an underfill material with build-in flux and is opportunistically included here to assess its fit for use for our future products. Overall DOE plans shall be described, preliminary results as well as the screening test plan will be presented in some detail and implication of these interacting factors in improving a SiP design to achieve small form end product will be discussed.