Flip Chip Solder Joint Pad Optimizations for a Connectivity SiP Application

Abstract

System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever thinning products is continuously pushing development of new materials, components and assembly technologies. This presentation focuses on a SiP flip chip (FC) pad design optimization study for connectivity applications. Original FC SiP design utilizes a solder-on-pad (SOP) pad design for SnAg bumped dice and such a design adds significant cost to the substrates for our cost sensitive connectivity applications. In addition, updated silicon's are also being bumped with copper-pillar (CuP) bumps and this has opened up opportunities to assess alternative low cost FC solder pad finishes, along with other substrate technologies. Following shall be discussed in this presentation: 1. A 6L substrate design with SOP and Non-SOP (NSOP) pads finishes (both with SMD & nominal component spacing); a modified 4L substrate design with NSOP pads, with ETS top layer & coreless (CL) and tighter component spacing: one with SMD pad design and the other NSMD 2. Assemblies of different substrates with two different types of FC bumps: copper pillar and SnAg and different MUF materials 3. Solder joint formation details with different pad finishes and resulting warpage behavior of the combination assemblies including type 5 solder paste printing using micro-stencil for FC assembly 4. MSL3 preconditioning and accelerated stress testing (1000 cycles from -55C to 125C) results and performances of different pad finishes 5. Failure analysis results and root cause investigations. Pad optimization is important for SiP applications: with solder mask define pads (SMD), we have a well-defined area for solder bump formation; however, solder mask itself occupies vertical space and for small SnAg or short CuP bumps this may present a challenge to the MUF flow to fill the die-to-substrate gap (the MUF used include both regular filler and reduced filler sizes). Furthermore, without SOP it is commonly believed that voiding may be an issue when solder ball diameter exceeds the SMD opening to trap airs during reflow process. On the other hand, NSMD pad designs have less control over where the melted solder flow and could present shorting challenges if not designed properly. Finally, ETS (embedded trace substrate) technology has proven itself to have significantly improved routing density and bond-on-trace flexibility. It is typically used for FCCSP applications with layer count & cost reduction potential. Here we port our modified design to a coreless substrate stack-up that also includes a top ETS layer with both SMD and NSMD pad finish to help assess the fit-for-use of the new substrate technology with different pad finishes for connectivity applications.