Impact of FCBGA substrate stack-up on BLR performance

Abstract

Board level reliability (BLR) temperature cycling is a metric for FCBGA field performance, where it is imperative to understand process variation holistically covering both substrate and / or assembly manufacturing process and its impact to product margin. This study focuses on technical reasoning a common FCBGA design manufactured with an identical substrate material set (i.e. core, dielectric, solder mask), assembly bill-of-materials (i.e. underfill, lid, etc.) and assembly site demonstrated different cycles to first failure during BLR testing. Although results far exceeded JESD22-A104 condition G requirements, BLR performance based on identical substrate designs (manufactured at different points in time) proved TV1 (test vehicle 1) performed ~2x better than its TV2 (test vehicle 2) counterpart. To elucidate the primary factor of the disparity in BLR performance, supplier feedback as well as a detailed package construction analysis ensued to compare build-up substrate layer thickness dimensions between TV1 and TV2. Discovery demonstrated a slightly larger volume of a specific layer in the build-up stack within TV2 that generated a higher degree of out-of-plane displacement as compared to TV1. Reproducing the cycles to first failure with the superior TV1 device via the TV1a and impact of substrate warpage was investigated as a factor in the BLR findings driving root cause.