Abstract

350um bump pitch is trend for Fan-Out (FO) package and wafer-level-chip-scale package (WLCSP) to reduce package size. 220um or 230um ball grid array (BGA) ball is used for package with 350um bump pitch. Board level reliability (BLR) test is standard qualified method for new package design. BLR test items of FO package and WLCSP are comprised of temperature cycling test (TCT) and drop test. However, BGA ball size reduction will increase ball stress and worsen BLR test result, comparing to 250um BGA ball with 400um bump pitch. How to improve BLR performance of package with 350um bump pitch is key design character. In this study, Fan-out single die (FOSD) package is selected to do BLR study and is comprised of one redistribution layer (RDL), one under bump metal (UBM) layer, and two passivation layers. Fan-in die size is 6.6mm x 6.6mm embedded into 7mm x 7mm FOSD package. Polyimide (PI) is used for passivation layers. UBM pad size, BGA ball size, and 2nd passivation layer thickness (PI-2) are selected as key factors to improve BLR performance. Ball stress and UBM neck stress simulations are used to select FOSD package structure with best BLR performance. From stress simulation results, UBM size is the most important factor, and PI-2 thickness and BGA ball size are second and third ones. 5% UBM diameter increase can reduce 14% ball stress and 37% UBM neck stress. 30% PI-2 thickness increase can reduce 9% ball stress and 37% UBM neck stress. 5% BGA ball diameter increase can reduce 4% ball stress but increase 5% UBM neck stress. BLR tests are comprised of TCT condition G (-40~125°C) and drop test 1500G. From BLR test results, PI-2 thickness is the most important factor, and UBM size and BGA ball size are second and third ones. 30% PI-2 thickness increase can increase 28% Drop performance and 87% TCT performance. 5% UBM diameter increase can reduce 16% Drop performance but increase 19% TCT performance. 5% BGA ball diameter increase can reduce both 15% Drop performance and 7% TCT performance.

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