Understanding the Effects of Process Parameters to Compensate for Substrate Warpage in Chip on Flex (CoF) Assembly Using Conventional Reflow

Abstract

Abstract Mounting rigid silicon (Si) die on a flex substrate presents a unique set of challenges. Substrate surface flatness and warpage of the flex substrate before and during thermal processing being two of the biggest issues. Various processes such as thermocompression bonding using anisotropic conductive films and thermosonic bonding using non-conductive adhesives have been shown to be effective for chip on flex (CoF) applications. However, these processes sacrifice process throughput and are less cost effective. Hence these methods may not be suitable for high volume manufacturing (HVM). For this reason, a process that is suitable for HVM and uses standard reflow processes and equipment is highly desirable. This works presents preliminary results for such a CoF process that uses a simple fixture and standard processes, materials and equipment. CoF process for Si die using two types of interconnects, solder balls or Cu pillars, was developed. Solder paste was stencil printed before pick and place of the Si die to offset the lack of flex substrate flatness and substrate warpage. The effect of stencil aperture diameter and placement force on process yield and stand-off height was studied. It was demonstrated that high yield can be obtained with a process that uses wider stencil aperture opening for both type of interconnects investigated. It was also observed that the placement force did not have any effect on process yield or stand-off height. The process can also be easily scaled up for HVM.