Static Random Access Memory Research Articles

Expanded Noise Margin 10T SRAM Cell using Finfet Device

Static random access memory (SRAM) cells are being improved in order to increase resistance to device level changes and satisfy the requirements of low-power applications. A unique 10-transistor FinFET-based SRAM cell with single-ended read and differential write functionality is presented in this study. This cutting-edge architecture is more power-efficient than ST (Schmitt trigger) 10T or traditional 6T SRAM cells, using only 1.87 and 1.6 units of power respectively during read operations. The efficiency is attributable to a lower read activity factor, which saves electricity. The read static noise margin (RSNM) and write static noise margin (WSNM) of the proposed 10T SRAM cell show notable improvements over the 6T SRAM cell, increasing by 1.67 and 1.86, respectively. Additionally, compared to the 6T SRAM cell, the read access time has been significantly reduced by 1.96 seconds. Utilising the Cadence Virtuoso tool and an 18nm Advanced Node Process Design Kit (PDK) technology file, the design's efficacy has been confirmed. For low-power electronic systems and next-generation memory applications, this exciting 10T SRAM cell has a lot of potential.

Single Event Upset Study of 22 nm Fully Depleted Silicon-on-Insulator Static Random Access Memory with Charge Sharing Effect.

In this paper, the single event effect of 6T-SRAM is simulated at circuit level and device level based on a 22 nm fully depleted silicon-on-insulator (FDSOI) process, and the effects of charge sharing and bipolar amplification are considered in device-level simulation. The results demonstrate that, under the combined influence of these two effects, the circuit's upset threshold and critical charge decreased by 15.4% and 23.5%, respectively. This indicates that the charge sharing effect exacerbates the single event effects. By analyzing the incident conditions of two different incident radius particles, it is concluded that the particles with a smaller incident radius have a worse impact on the SRAM circuit, and are more likely to cause the single event upset in the circuit, indicating that the ionization distribution generated by the incident particle affects the charge collection.

Radiation hardened 11T memory cell for space applications

Continuous nanometer technology scaling, along with rapid growth in the field of artificial intelligence (AI), internet-of-things (IoT), and other high-performance computing applications increases the need for low power and soft error immune VLSI circuits. Conventional radiation hardened bit cell such as QUATRO10T with partial single event upset (SEU) immunity and bit cells such as DICE12T, WE-QUATRO12T, and RHD13T needs large area and power consumption. To address these problems, a soft error immune radiation hardened memory cell 11T (RHMC11T) static random-access memory (SRAM) bit cell is proposed which is immune to both SEU and single event multiple node upsets (SEMNU) along with good read and write stability. The enhancement in the key parameters of the proposed cell is confirmed by comparing the proposed bit cell with the conventional bit cells such as 6T, NS10T, PS10T, QUATRO10T, RHMD10T, RHBD10T, 11T, and 12T. The critical charge of the proposed RHMC11T is improved by 43%, 27%, 19%, 2%, 2%, and 4% while comparing with 6T, NS10T, PS10T, QUATRO10T, RHBD10T, and 11T. The proposed bit cell has higher SVNM of 49%, 19%, 11%, 8%, and 5% and smaller WTV of 50%, 33%, 23%, 18%, and 21% compared to 6T, PS10T, RHMD10T, RHBD10T, and 12T respectively. The proposed RHMC11T has lesser read access time of 63%, 50%, 46%, 6%, and 6% compared to NS10T, PS10T, QUATRO10T, RHMD10T, and 11T. The proposed RHMC11T bit cell with dedicated write and read word lines makes it applicable for bit interleaving architecture and also it satisfies reliability requirements making it a good choice for highly radiative terrestrial environment applications such as in aerospace and satellites.

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications

This paper first presents a double-node upset (DNU) protected and sextuple cross-coupled static-random-access memory (SRAM) cell, i.e., SCCS-18T, for aerospace applications. The cell can recover from each possible single-node upsets (SNUs) as well as partial DNUs due to its formed large feedback loop that can retain values and intercept errors. To improve DNU self-recoverability, an enhanced version of the SCCS-18T cell, namely SCCS-18T-EV, is proposed. Due to the new formed structure, the SCCS-18T-EV can recover from more DNUs. Since parallel access transistors are used, the proposed cells have optimized read/write performance. Simulation results demonstrate the node-upset tolerance as well as the optimized operation performance of the proposed SCCS-18T and SCCS-18T-EV cells compared to existing SRAM cells.

Design and Analysis of Static Random-Access Memory FinFET Circuit Using Self Controlled Voltage Level Controller

Researchers in the field of device research are always searching for a device that meets certain criteria, such as having low leakage and a low threshold voltage, without sacrificing performance. This pursuit has led to the development of numerous gate architectures. As a result of the enormous size of the static random-access memory (SRAM), its yield and leakage power consumption account for the majority of the chip’s total yield and leakage power consumption respectively. However, as CMOS technology continues to grow in the sub-65 nanometer domain to lower the cost of transistors and the dynamic power, it presents a number of issues on the design of SRAM. In this paper, a 6T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 6T cell which uses high and low VTH transistors to improve the read and write stability. Also, the changes of cell parameters when the temperature rises from 40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell are studied at two supply voltages of 400 mV and 500 mV.

Reconfigurable negative bit line collapsed supply write-assist for 9T-ST static random access memory cell

<span lang="EN-US">This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in write margin (WM), 0.96×, 0.89× and 0.72× minimum write trip-point (WTP) from transient-negative bit line (Tran-NBL), capacitive charge sharing (CCS), and conventional write circuits respectively. The proposed RNBLCS is functionally verified using a synopsys custom compiler with a 16 nm BSIM4 model card for bulk complementary metal-oxide semiconductor (</span><span lang="EN-US">CMOS).</span>

Near-Threshold Wide-Voltage Design Review

This paper presents a comprehensive review of near-threshold wide-voltage designs on memory, resilient logic designs, low voltage Radio Frequency (RF) circuits, and timing analysis. With the prosperous development of wearable applications, low power consumption has become one of the primary challenges for IC designs. To improve the power efficiency, the prefer scheme is to operate at an ultra low voltage of Near Threshold Voltage (NTV). For the performance variation and degradation, a self-adaptive margin assignment technique is proposed in the low voltage. The proposed technique tracks the circuit states in real time and dynamically allocates voltage margins, reducing the minimum supply voltage and achieving higher energy efficiency. The self-adaptive margin assignment technique can be used in Static Random Access Memory (SRAM), digital circuits, and analog/RF circuits. Based on the self-adaptive margin assignment technique, the minimum voltage in the 40 nm CMOS process is reduced to 0.6V or even lower, and the energy efficiency is increased by 3–4 times.

Total Ionizing Dose Response of a 22-nm Compiled Fully Depleted Silicon-on-Insulator Static Random Access Memory

The results of total ionizing dose (TID) experiments on fully-depleted silicon-on-insulator (FDSOI) static random access memory (SRAM) are presented. Using <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> Co gamma irradiation, tests were conducted at multiple voltages and with and without read and write assists. The results demonstrate cell stability past 200 krad(Si) TID in standard operational modes. The impact of read and write assists and read timing via margin mode tests are examined. We also report input-output (IO) level translation circuit failures, as well as anomalous circuit failures attributable to IO at relatively low TID dose. Finally, we show post-TID anneal and low voltage SRAM results.

PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing

With the rapid development of the Internet of Things (IoT), compute-in-memory (CIM) is a promising candidate for edge computing, which eliminates the need for frequent data transfer between the memory and processing units. On one hand, CIM provides an efficient approach to achieve deep neural network (DNN) inference; on the other hand, its security issues such as model leakage are ignored in most of state-of-the-art studies. In the resource-limited conditions, it is essential to develop a lightweight secure scheme for CIM without significantly sacrificing its performance. In this work, a physical unclonable function (PUF)-CIM macro based on static random access memory (SRAM) is proposed for lightweight model protection. An SRAM-based PUF extracts unique and stable keys from the mismatch of multirow discharge rate and further achieves zero bit error rate (BER) under temperature and voltage fluctuations by the on-chip masking technique. Besides, we propose a 10T SRAM bit cell to perform xor operation and multiply-and-accumulate (MAC) operation in the same cell, which avoids weight movement during encryption and decryption. The whole process including key generation, xor encryption, and ciphertext MAC operation has been realized. The test chip is designed and fabricated in a 55-nm CMOS process. Experimental results show that the proposed PUF with on-chip masking can provide zero unstable bits and BER under temperature and voltage variations. The proposed PUF-CIM achieves 96.20% inference accuracy in MNIST. Besides, it presents 93.35–121.38-TOPS/W energy efficiency and 1324.24-GOPS throughput. Compared with the normal CIM, the proposed PUF-CIM can enhance AI model security, only with accuracy loss of 1% and energy efficiency degradation of 16.1%.

Electronics Irradiation With Neutrons at the NEAR Station of the n_TOF Spallation Source at CERN

We study the neutron field at the NEAR station of the neutron time of flight (n_TOF) facility at CERN, through Monte Carlo simulations, well-characterized static random access memories (SRAMs) and radio-photo-luminescence (RPL) dosimeters, with the aim of providing neutrons for electronics irradiation. Particle fluxes and typical quantities relevant for electronics testing were simulated for several test positions at NEAR and compared to those at the CERN high energy accelerator mixed-field facility (CHARM), highlighting similitudes and differences. The SRAM detectors, based on single event upset (SEU) and single event latch-up (SEL) counts, each one with a different energy response, and RPL dosimeters were tested in a reference position and the results were benchmarked to FLUKA simulations. Finally, the neutron spectra at NEAR are compared to those of the most well-known spallation sources and typical environments of interest, for accelerator and atmospheric applications, showing the potential of the facility for electronics irradiation.

An Analysis of the Significance of the 14N(n, p) 14C Reaction for Single-Event Upsets Induced by Thermal Neutrons in SRAMs

The thermal neutron threat to the reliability of electronic devices caused by <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> B capture is a recognized issue that prompted changes in the manufacturing process of electronic devices with the aim of limiting as much as possible the presence of this isotope nearby device sensitive volumes. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> N can also capture thermal neutrons and release low-energy protons (through the <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> N(n,p) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> C reaction) that have high enough linear energy transfer to cause single-event upsets (SEU). Typically, nitrogen is used in thin barrier layers made of TaN or TiN or even as insulator in the form of Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> . Numerical simulations on sensitive volumes calibrated on proton and ion experimental data and with an accurate description of the metallization layer on top of the sensitive region show that the presence of nitrogen in these thin barrier layers can be enough to justify the experimentally observed thermal neutron SEU cross section for a static random access memory sensitive to low-energy protons. Nevertheless, the expected SEU cross section from thermal neutrons is usually a few orders of magnitude lower than that of high-energy particles, therefore, not representing an important threat in atmospheric applications. At the same time, for high-energy accelerators, the contribution to the total soft error rate could become substantial, though easy to handle by margins.

A low-power SRAM design with enhanced stability and ION/IOFF ratio in FinFET technology for wearable device applications

ABSTRACT Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transistor (SE10T) SRAM cell with high stabilities. It utilises a stacked pull-down structure for hold/read stability improvement and leakage power reduction, a feedback-cutting mechanism for writability enhancement, and single-ended read/write structures for dynamic power reduction. Also, using a single-transistor reading path with eliminated read bitline leakage enhances ON-to-OFF currents (I ON /I OFF ) ratio. The proposed design is compared with the conventional 6T, Schmitt-trigger 10T (ST10T), differential writing 10T (DW10T), data-independent read port 10T (DIRP10T), transmission gate read-decoupled 9T (TGRD9T), and feedback-cutting 11T (FC11T) SRAM cells based on 7-nm Fin-shaped Field-Effect Transistor (FinFET) technology at V DD = 0.4 V. The proposed design shows at least 1.04×/1.01×/1.12×/1.25×/1.15× improvement in read stability/writability/read delay/leakage power/dynamic power. Moreover, it shows at least 1.22× improvement in I ON /I OFF ratio and offers the lowest minimum operating voltage (0.292 V). However, it offers a 1.02× lower hold stability than that of ST10T, a 1.18×/1.14×/1.13× higher write delay compared to 6T/ST10T/DW10T, and a 1.56×/1.07×/1.05× higher layout area occupation in comparison with 6T/TGRD9T/DIRP10T. Therefore, the proposed SRAM cell can be an optimum candidate for usage in smartwatches.

Propagation Delay and Power Dissipation Analysis for a 2-Bit SRAM Using Multi-State SWS Inverter

This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.

Compute-in-Memory SRAM Cell Using Multistate Spatial Wavefunction Switched (SWS)-Quantum Dot Channel (QDC) FET

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices.

Fabrication of Multi-Bit SRAMs Using Quantum Dot Channel (QDC)-Quantum Dot Gate (QDG) FET

This paper presents fabrication of multi-state inverters incorporating SiOx-cladded Si quantum dot in the channel and gate region of driver, load, and access transistors. Experimental characteristics are presented exhibiting 3-state behavior in Quantum-dot Channel (QDC)-Quantum-dot Gate (QDG) FETs having Si quantum dots. It is shown that QDC-QDG-FETs-based enhancement mode inverter configurations are the building blocks of a multi-bit static random access memory (SRAM). QDC-QDG-FETs exhibiting four states can also be used to implement compact 4-state logic and nonvolatile memories or random access nonvolatile memories.

A high-speed and power-efficient gradient-pulse injection method for spin-transfer torque magnetic random-access memory

With the development of modern computer storage technology, the spin-transfer torque magnetic random-access memory (STT-MRAM) has become one of the most promising candidates to replace the static random-access memory and dynamic random-access memory. However, its large power consumption and long relaxation time before the magnetic moments switch are important factors restricting its commercial application. In this work, gradient-current pulses are proposed to replace the conventional constant-current pulses in the injection method. A 70-nm classical CoFeB/MgO/CoFeB magnetic tunnel junction (MTJ) with perpendicular magnetic anisotropy was simulated and measured at pulse widths of 20, 30, and 40 ns using the proposed and conventional injection pulses. The comparison results show that adopting gradient pulses can significantly reduce the relaxation time and switching power consumption of the MTJ. A power consumption reduction of 8%–40% is obtained at different pulse amplitudes and widths. Our method paves an avenue for overcoming the issues affecting the STT-MRAM and could help to promote its commercial applications.

Leakage power attack resilient Schmitt trigger based 12T symmetric SRAM cell

In this paper, a new 12T Schmitt trigger based SRAM cell is proposed in 40 nm technology. The proposed SRAM cell is resilient to leakage power attack (LPA), which is one of the main concern in side-channel attack (SCA). The proposed SRAM cell is designed by incorporating two more transistors to the Schmitt Trigger based 10T SRAM cell and is having equal leakage current when the storage node (Q) is storing 0 and 1, thereby achieving the overall distribution overlap percentage of 97.5% as compared to 0.09% of overlap in case of Schmitt Trigger based 10T SRAM. The Hold Static Noise Margin (HSNM), Read Static Noise Margin (RSNM) and Write Margin (WM) of the proposed design are also increased by 38.14%, 58.11% and 20.29% respectively as compared to 6T. Moreover, the WTP of the LPAR 12T is 1.07× greater as compared to the conventional 6T SRAM cell.

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver

A 0.7-pJ/bit, 8.5-Gb/s/link inductive coupling interchip wireless communication interface for a 3D-stacked static-random access memory (SRAM) has been developed in a 7-nm FinFET process. A new physical placement method that allows coils to be placed over off-the-shelf SRAM macros with small magnetic field attenuation, together with the use of synchronous communication using Manchester encoding and a clocked comparator to enable the detection of small-swing signals, achieves a 26% reduction in SRAM die area compared to through-silicon via (TSV)-based stacking. Interchip communication at 0.7 pJ/bit, 8.5 Gb/s/link was confirmed using test chips. A 4-hi 3D-stacked SRAM module using the proposed interface achieves a 1.2-TB/s/mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> area efficiency, representing a two orders-of-magnitude improvement over the state-of-the-art 3D-stacked SRAM.

RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems

Magnetic random access memory (MRAM) is considered one of the most promising memories among nonvolatile memories (NVMs), to replace static random access memory (SRAM) in the computing system to improve its cache performance. In this article, performance evaluation and strategy exploration of three-level hybrid cache systems are conducted under the framework of Reduced InstrucTIon Set Computer-Five (RISC-V) instruction set. First, system-level joint calls of Nvsim, Gem5, McPAT, and other cache emulation architectures are implemented based on the system-level simulator called MAGPIE tool. Based on the performance comparison of spin transfer torque (STT)-MRAM, spin-orbit torque (SOT)-MRAM, and SRAM with varied capacities, a variety of combined CPU three-level hybrid cache architectures are simulated. The performances of the proposed hybrid cache systems and the bus impact of interconnecting are evaluated, with better analysis of the cost of CPU system implementation and interactions among levels of cache. The power consumption of different processors with various instruction sets and cores is also evaluated. It is demonstrated that SOT-MRAM and STT-MRAM show great potential applications as L2 and L3 caches in the RISC-V system. RISC-V shows the potential benefits for future CPU cache. Meanwhile, an adaptive stride prefetching strategy is proposed to address the problem of delay hysteresis and high miss rate of STT-MRAM in the L3 cache. The applicability of this strategy to different storage technologies and the comparison with cutting-edge technologies are also illustrated. Simulation results show that the prefetching strategy can achieve at most 64.12% and 94.55% optimization effects on the miss latency and the miss rate of L3 cache, respectively.

3D SRAM Macro Design in 3D Nanofabric Process Technology

In this paper, we introduce a novel design of a 3D static random-access memory (SRAM) macro in a 3D Nanofabric process technology. The 3D Nanofabric technology is based on enabling the processing of N stack of identical layers simultaneously regardless of the number of stacked layers which consequently reduces the fabrication cost as well as the footprint of SRAM macros. To enable simultaneous patterning of stacked layers, 3D Nanofabric requires circuit topology and layout that rely on a single layer where the device channel, poly, and metal wires are all embedded without any other crossing than the gate on top of the device channel. Accordingly, we modify the layouts of the conventional SRAM bit-cell and periphery circuits which are complex and contain several metal crossings. Furthermore, we propose a new overall organization of the 3D SRAM macro that incorporates a stack of multiple identical layers each consisting of an equal size 2D array of bit-cells and the periphery circuits. We show that the proposed 3D Nanofabric SRAM macro offers 71.2% footprint gain and 36.3% read access speed improvement compared to equal size 2D SRAM macro in 3 nm FinFET.