RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems

Abstract

Magnetic random access memory (MRAM) is considered one of the most promising memories among nonvolatile memories (NVMs), to replace static random access memory (SRAM) in the computing system to improve its cache performance. In this article, performance evaluation and strategy exploration of three-level hybrid cache systems are conducted under the framework of Reduced InstrucTIon Set Computer-Five (RISC-V) instruction set. First, system-level joint calls of Nvsim, Gem5, McPAT, and other cache emulation architectures are implemented based on the system-level simulator called MAGPIE tool. Based on the performance comparison of spin transfer torque (STT)-MRAM, spin-orbit torque (SOT)-MRAM, and SRAM with varied capacities, a variety of combined CPU three-level hybrid cache architectures are simulated. The performances of the proposed hybrid cache systems and the bus impact of interconnecting are evaluated, with better analysis of the cost of CPU system implementation and interactions among levels of cache. The power consumption of different processors with various instruction sets and cores is also evaluated. It is demonstrated that SOT-MRAM and STT-MRAM show great potential applications as L2 and L3 caches in the RISC-V system. RISC-V shows the potential benefits for future CPU cache. Meanwhile, an adaptive stride prefetching strategy is proposed to address the problem of delay hysteresis and high miss rate of STT-MRAM in the L3 cache. The applicability of this strategy to different storage technologies and the comparison with cutting-edge technologies are also illustrated. Simulation results show that the prefetching strategy can achieve at most 64.12% and 94.55% optimization effects on the miss latency and the miss rate of L3 cache, respectively.