Radiation hardened 11T memory cell for space applications

Abstract

Continuous nanometer technology scaling, along with rapid growth in the field of artificial intelligence (AI), internet-of-things (IoT), and other high-performance computing applications increases the need for low power and soft error immune VLSI circuits. Conventional radiation hardened bit cell such as QUATRO10T with partial single event upset (SEU) immunity and bit cells such as DICE12T, WE-QUATRO12T, and RHD13T needs large area and power consumption. To address these problems, a soft error immune radiation hardened memory cell 11T (RHMC11T) static random-access memory (SRAM) bit cell is proposed which is immune to both SEU and single event multiple node upsets (SEMNU) along with good read and write stability. The enhancement in the key parameters of the proposed cell is confirmed by comparing the proposed bit cell with the conventional bit cells such as 6T, NS10T, PS10T, QUATRO10T, RHMD10T, RHBD10T, 11T, and 12T. The critical charge of the proposed RHMC11T is improved by 43%, 27%, 19%, 2%, 2%, and 4% while comparing with 6T, NS10T, PS10T, QUATRO10T, RHBD10T, and 11T. The proposed bit cell has higher SVNM of 49%, 19%, 11%, 8%, and 5% and smaller WTV of 50%, 33%, 23%, 18%, and 21% compared to 6T, PS10T, RHMD10T, RHBD10T, and 12T respectively. The proposed RHMC11T has lesser read access time of 63%, 50%, 46%, 6%, and 6% compared to NS10T, PS10T, QUATRO10T, RHMD10T, and 11T. The proposed RHMC11T bit cell with dedicated write and read word lines makes it applicable for bit interleaving architecture and also it satisfies reliability requirements making it a good choice for highly radiative terrestrial environment applications such as in aerospace and satellites.