Spacer Width Research Articles

Magnetization States and Coupled Spin-Wave Modes in Concentric Double Nanorings.

Concentric multiple nanorings have previously been fabricated and investigated mainly for their different static magnetization states. Here, we present a theoretical analysis for the magnetization dynamics in double nanorings arranged concentrically, where there is coupling across a nonmagnetic spacer due to the long-range dipole-dipole interactions. We employ a microscopic, or Hamiltonian-based, formalism to study the discrete spin waves that exist in the magnetic states where the individual rings may be in either a vortex or an onion state. Numerical results are shown for the frequencies and the spatial amplitudes (with relative phase included) of the spin-wave modes. Cases are considered in which the magnetic materials of the rings are the same (taken to be permalloy) or two different materials such as permalloy and cobalt. The dependence of these properties on the mean radial position of the spacer were studied, showing, in most cases, the existence of two distinct transition fields. The special cases, where the radial spacer width becomes very small (less than 1 nm) were analyzed to study direct interfaces between dissimilar materials and/or effects of interfacial exchange interactions such as Ruderman-Kittel-Kasuya-Yoshida coupling. These spin-wave properties may be of importance for magnetic switching devices and sensors.

Tunneling Valley Hall Effect Driven by Tilted Dirac Fermions.

Valleytronics is a research field utilizing a valley degree of freedom of electrons for information processing and storage. A strong valley polarization is critical for realistic valleytronic applications. Here, we predict a tunneling valley Hall effect (TVHE) driven by tilted Dirac fermions in all-in-one tunnel junctions based on a two-dimensional (2D) valley material. Different doping of the electrode and spacer regions in these tunnel junctions results in momentum filtering of the tunneling Dirac fermions, generating a strong transverse valley Hall current dependent on the Dirac-cone tilting. Using the parameters of an existing 2D valley material, we demonstrate that such a strong TVHE can host a giant valley Hall angle even in the absence of the Berry curvature. Finally, we predict that resonant tunneling can occur in a tunnel junction with properly engineered device parameters such as the spacer width and transport direction, providing significant enhancement of the valley Hall angle. Our work opens a new approach to generate valley polarization in realistic valleytronic systems.

Effect of parabolic structure potentials on electron mobility in AlxGa1-xAs quantum well based field effect transistor structure

Here, we theoretically calculate and analyze electron mobility μ in AlxGa1-xAs double parabolic and semi-parabolic quantum well (DPQW and DSPQW) based field effect transistor structures. We compute μ as a function of applied electric field F by considering ionized impurity (II) and alloy disorder (AL) screened scattering potentials (VscrII/AL) and show that μ(DPQW) > μ (DSPQW). The symmetric property of VscrII/AL makes μ to vary symmetrically around F = 0 at which two subbands are occupied. The shape of the DSPQW structure potential, compared to DPQW, causes the subband wave functions ψ0 and ψ1 to lie nearer and also penetrate more into the central barrier. Accordingly, the II-scattering is reduced due to increased distance of the electrons from the ionized donors (lying in the side barriers), while AL-scattering is enhanced through increased scattering in the central barrier. As a result, we obtain for F = 0, μII (DSPQW) > μII (DPQW) and μAL (DSPQW) < μAL (DPQW). Further, we show that μ enhances in DPQW by increasing design parameters such as well width, spacer width, and central barrier width. However, μ reduces with the increase in alloy concentrations inside the well through intersubband interaction. The obtained results reflect the suitability of parabolic potential based quantum well structures in emerging optoelectronic devices to enhance the transport and optical properties.

300 mm integration of a scalable phase change material spacer by inductively coupled plasma etching

To improve the heating efficiency and reduce the reset current of phase change memory, the volume-confined cells have been widely studied by employing highly conformal deposition techniques. In this work, a scalable confined structure with sidewall phase change material spacer is investigated for the integration in 12-inch wafer using physical vapor deposition and the subsequent anisotropic plasma etching back process. The finite element simulations reveal a remarkable 80% increase in heating efficiency by taking the confined structure. The isolated and compact trenches with the aspect ratio ranging from 0.40 to 1.04 are designed to accommodate the sidewall phase change material. The scaling down of the critical dimension of the rail-like spacer is observed as the aspect ratio increases. The spacer width of around 34 nm is well beyond the lithography capability used in this study. These results provide a promising path to fabricate the low-power and high-density memory device in a way fully compatible with the manufacturing technology.

Quantum Effect Dependent Modelling of Short Channel Junctionless Double Gate Stack(SC-JL-DG) MOSFET for High Frequency Analog Applications

In this paper, the quantum effect has been induced on Junctionless (JL)-Double Gate metal-oxide-semiconductor field-effect transistors (JL-DGMOSFET) with gate oxide stack to study its effect on different device parameters like surface potential, threshold voltage, Id, Vg, gm, channel length etc. The study has been extended on Ion/Ioff change w.r.t. the variation in spacer width for varied channel thickness. In order to extend the efficacy of the results an analytical model has been formulated. The analytical model is developed by incorporating the Schrodinger equation in the conventional 2-D Poisson's equation, which has further been solved by applying the boundary conditions to obtain the final expression for potential and change in threshold voltage (Vth). The device parameters are in accordance for both the simulated and analytical results. The simulation work has been supported by the ATLAS device simulation.

Safety of hydrogel spacers for rectal wall protection in patients with prostate cancer: A retrospective analysis of 200 consecutive cases.

To evaluate the safety and complications of hydrogel spacer implantation. This single-center historical cohort study retrospectively analyzed cases of hydrogel spacer implantation between October 2018 and March 2022. The survey items were the rates of possible hydrogel injection implementation, the success rate of hydrogel implantation including asymmetry, higher position, rectal wall infiltration, subcapsular injection, and other adverse events, and width created by the spacer. To investigate the learning curve, 1, 2, and 3 points were assigned to adverse event grades G1, G2, and G3, respectively. Spacer effectiveness obstruction, such as asymmetry was assigned 3 points. A Mann-Whitney U test was performed to assess statistically significant differences. The study included a total of 200 patients with a median (range) age of 70 (44-85) years. In 10 (5%) patients, hydrogel injection implementation was not possible. Of 190 patients who underwent hydrogel spacer placement, 168 (88%) received a satisfactory placement. The median (range) width of hydrogel spacers was 13.1 (4.4-18.7) mm. Spacer asymmetry, higher position, rectal wall infiltration, and prostate subcapsular infiltration occurred in 7 (3.7%), 5 (2.6%), 12 (6.3%), and 1 (0.5%) patients, respectively. G1 and G3 adverse events occurred in 13 (7%) and 4 (2%) patients, respectively. Practitioner #1 who performed the highest number of procedures had significantly (p=0.04) lower total scores in group B. Spacer implantation yielded favorable outcomes with a high percentage of appropriate spacer implantation, and few major complications.

Electric field induced non-monotonic electron transport in pseudomorphic Al0.3Ga0.7As/In0.15Ga0.85As coupled quantum well structure

In this article, the non-monotonic electron mobility (μ) is modulated by applying an external electric field (Fext) in pseudomorphic Al0.3Ga0.7As/In0.15Ga0.85As asymmetric coupled quantum well (ACQW) structure. The structural asymmetry is achieved through dissimilar doping in the side barriers. Application of a specific Fext (here, Fext = 6.66 kV/cm) makes the proposed structure potentially symmetric causing resonance of subband states (RSS) between the wells. Near resonance, the drastic change in the distribution of subband wave functions leads to cusp like variation of the scattering rate matrix elements resulting non-monotonic nature of μ. We show that the variation of μ is mostly due to the ionized impurity scattering mediated by intersubband effects. However, there is a sudden drop in mobility due to interface roughness scattering i.e., μir at RSS and subsequently, it reduces the overall magnitude of μ. We show that μ can be enhanced with a sharp drop at the resonance point by increasing the well width, central barrier width, spacer width, or doping region width of the proposed structure. The results obtained can be utilized to improve the performance of negative resistance based low dimensional device structures.

PP10 Presentation Time: 11:00 AM: Assessment of NASHA Spacer Symmetry for Prostate Radiation Therapy

<h3>Purpose</h3> NASHA (non-animal stabilized hyaluronic acid) is a spacer that can increase the separation between the prostate and anterior rectal wall prior to prostate radiation therapy (RT). Since there is no pre-defined time limit for NASHA spacer injection, physicians can precisely distribute the product within the peri-rectal space. Furthermore, the spacer is highly visible on T2-weighted MR, and generally visible on CT with optimized view settings. We conducted a randomized controlled trial evaluating whether a NASHA spacer improves rectal dosimetry among patients receiving hypofractionated RT (NCT 04189913). The purpose of the study is to evaluate the symmetry of a NASHA spacer among all patients who received the device on that study. <h3>Materials and Methods</h3> We analyzed data for 131 of 136 patients, who were randomized to and received a NASHA spacer on trial (5 datasets were unavailable at the time of analysis). All patients had pre-implant and post-implant CT/MR simulation. We developed an automated system for evaluating symmetry based on a previously published method (Fischer-Valuck, PRO, 2017). Briefly, prostate, rectum and spacer contours that had been prospectively validated by a core laboratory were downloaded. From the prostate center-of-mass, we defined axial slices at mid-gland, 1-cm superior, and 1-cm inferior. For each axial slice, we calculated the center of the spacer (spacer width center) along the transverse axis. Axial slice symmetry scores were assigned based on the distance between the spacer width center and the prostate midline (1 = distance within 1 cm of midline (symmetric), 2L/2R = distance between 1-2 cm from midline, 3L/3R = distance more than 2 cm from midline). Patient-level symmetry scores were assigned based on the number of slices with an asymmetric distribution (1 = none, 2 = 1 of 3 slices with axial score of 2L/2R, 3 = 2 of 3 slices with axial score of 2L/2R, 4 = all 3 slices with axial score of 2L/2R). <h3>Results</h3> The percentages of patients with an axial slice symmetry score of 1 (symmetric) at mid-gland, superior, and inferior planes, were 97%, 98%, and 98%, respectively (see Figure). Following the Fischer rubric, planes without gel were omitted (N=2 mid-gland, N=2 superior and N=9 inferior planes). The percentage of patients with patient-level symmetry scores of 1, 2, 3 and 4, were 95.4%, 2.3%, 1.5%, and 0.8% respectively. <h3>Conclusions</h3> Over 95% of NASHA spacers placed in this prospective trial demonstrated patient-level symmetry. These results suggest that NASHA may also improve rectal dosimetry for prostate brachytherapy. Further study is ongoing to correlate the dosimetry and clinical outcomes to implant quality for these patients.

Comparing bulk-Si FinFET and gate-all-around FETs for the 5 ​nm technology node

In this paper, bulk CMOS finFET, horizontal gate-all-around (GAA) nanowire and nanosheet field-effect transistors are compared for the 5 ​nm technology node. The performance of these transistors and the circuits comprising them is assessed through 3-D technology computer-aided design (TCAD) simulations and circuit level SPICE simulations of BSIM compact models calibrated to the TCAD results, respectively. Full parasitic extraction is used on standard cell and static random access (SRAM) memory cell layouts to ensure accurate delays. The target of this work is a 5 ​nm technology node follow-on to an existing 7 ​nm predictive process design kit (PDK) in common academic use. Subthreshold slope, drain induced barrier lowering, gate-induced drain leakage and subthreshold current are compared for different gate lengths. Transistor performance is also compared for various raised source/drain lengths and low-k gate spacer widths. The gate-all-around field-effect transistors show better electrostatic performance as expected. However, the simulation results show that finFET devices will be adequate at the 5 ​nm node, should the GAA devices prove to be difficult to produce in high volume manufacturing.

Modeling and simulation of gas separations with spiral‐wound membranes

AbstractModels for gas separations with spiral‐wound membranes are developed and found to exhibit good agreement with experiments performed on N2/O2 mixtures. The two‐dimensional (2D) model can be accurately approximated by a one‐dimensional (1D) surrogate model when the spacer widths are chosen to make the channel pressure drops small. Subsequently, the separation of propane/propylene mixtures from the recycle purge stream of a polypropylene reactor is investigated. Assuming ideal gas is found to lead to significant overestimations in membrane stage cuts (sometimes more than 10%), an extent comparable to that associated with extrapolating constant olefin permeance from a low‐pressure condition. While olefin permeance can change significantly with pressure, using a constant‐permeance formulation can result in a small (&lt; 2.5%) underprediction in stage cut if the value for the permeance is taken from the feed condition. Finally, membrane properties and costs necessary for a viable separation process are discussed.

Effect of Width of Axial Supporting Spacers on the Buckling Strength of Transformer Inner Winding

During a short circuit, the transformer's inner winding, which is supported by the inner support structure, may fail due to the buckling phenomenon. This occurs due to the generation of large radially inward electromagnetic force on the inner winding. In the literature, the effect of the number of axial supporting spacers on the critical buckling stress is reported, but there is no investigation about the effect of their circumferential width on the value of the critical buckling stress. In this letter, the effect of the circumferential width of the axial supporting spacers on the value of critical buckling stress of the transformer inner winding has been investigated. An algorithm has been given to calculate the critical buckling stress of the inner winding. A case study has been taken from the published work, and by varying the width of the spacers, the factor of safety against buckling has been determined.

Symmetric dual gate insulator‐based FinFET module and design window for reliable circuits

High-k spacer and gate insulator materials have been exhaustively studied nowadays for the enhancement of electrostatic control and reduction of short-channel effects in scaled devices. The work presents a high-performance and charge trap tolerant FinFET module at 10 nm gate length. Dual layer gate insulator (inner low-k and outer high-k) introduces to reduce charge trapping from the channel and outside into the gate oxide. It reduces the gate leakage current by 51.6% compared to conventional FinFET. Further, they demonstrate single charge trapping (SCT) induce effects and proposed optimised high-k spacer width of the SCT tolerant design. SCT analysis is presented in different high-k spacer materials and back-gate voltages. Process variation sources such as line edge roughness and line width roughness are also analysed for the circuit design.

Plasmon modes in bilayer-graphene–GaAs heterostructures including layer-thickness and exchange-correlation effects

We investigate the dispersion relation and decay rate of plasmon modes in a double-layer system made of bilayer graphene (BLG) and infinite GaAs quantum well at zero-temperature within the generalized random-phase-approximation and taking into account the 2DEG layer-thickness and inhomogeneity of the background dielectric. We illustrate that the acoustic plasmon dispersion curve of the considered system differs significantly from that of monolayer graphene (MLG)–GaAs heterostructure and BLG–GaAs without layer-thickness. Calculations also demonstrate that meanwhile the optical plasmon curve is affected slightly by spacer width and exchange-correlation, the acoustic one depends remarkably on the interlayer distance, inhomogeneity of the background dielectric, carrier densities, spacer dielectric constant, quantum well width and exchange-correlations.

Impact of high k spacer on RF stability performance of double gate junctionless transistor

AbstractIn this paper, radio frequency (RF) stability performance of double gate junctionless transistor for different spacer material, the width of spacer, and bias conditions is reported. The impact of gate oxide thickness and gate work function on RF performance of double gate junctionless transistor is also presented. The analog and RF figure of merit, namely, intrinsic gain, unity gain cut‐off frequency, stern's stability factor, critical frequency, maximum attainable gain, and maximum stable gain, are investigated with the help of numerical simulation. The result shows that the fringing fields of high k spacers have a major impact on the gate to source and gate to drain capacitance. The device design guideline along with bias and geometrical parameters are reported for the optimized structure. The optimized device structure exhibits better RF stability.

(Invited) Bicmos Technology Optimization for Millimeter Wave Applications

With the progress of RF CMOS and BiCMOS technologies, millimeter-wave applications have come well within reach of silicon-based technologies [1-3]. NXP’s SiGe BiCMOS process offers a 0.25μm CMOS base-line, with shallow- and deep-trench isolation, a full suite of high-quality passive components and three SiGe:C Heterojunction Bipolar Transistors. From the first publication on the 8th generation [4], the process architecture has only been changed cautiously, keeping manufacturability and cost very competitive. A good example of that is the addition of the third HBT with a high-energy implanted subcollector [5], bringing the typical BVCBO breakdown voltage range from 4.5V to 11.5 to 15V for the Low Voltage, High Voltage and Extended High Voltage device respectively. Generation 9 was first published in 2015 [6], with main features illustrated in Figs. 1 and 2. Since then, the process has been used to further explore millimeter-wave application needs. In this paper, we focus on improving noise performance at frequencies above 28GHz by scaling the npn in the vertical direction, i.e. the doping profiles, but also scaling in the lateral direction to reduce all parasitic elements. In the early nineties device fabrication using epitaxial growth of strained SiGe/Si heterostructures enabled a breakthrough in bipolar process technology. Nanometer-scale bandgap engineering of SiGe:C Heterojunction Bipolar Transistors have pushed fT/fMAX performances above 500GHz. In our technology today, non-uniformity of the thicknesses of the individual layers has been brought below 5Å, matched across a number of epi reactors in two different fabs. After growing the desired npn doping profile with such great care and precision, the total thermal budget of the BiCMOS process and all its options, determines to a great extent what performance is left of the intrinsic doping profile capability. The noise performance of a Low Noise Amplifier (LNA) depends on the minimum noise figure NFMIN=10log(FMIN) of the SiGe Heterojunction Bipolar Transistor (HBT), which in turn depends on a number of technology related device parameters, see Equation (1), [7]. F = 1 + 1/hFE + { 1/hFE + (2gmRB) (1/hFE + (f/fT)2 ) }1/2 ( 1 ) Building on the excellent base resistance properties of the non-selectively grown SiGe:C base architecture of Gen9, we have investigated in this work the effect of reducing the total temperature budget to enable shorter delay times. In a first experiment the final activation anneal was reduced in 5 steps to provide input on re-tuning of the thicknesses in the base-epi stack. From known correlations between inline ellipsometry and process control measurements like, for example reverse emitter-base breakdown voltage shown in Fig. 3, the temperature decrease on the activation anneal could be calculated to correspond with a delta of around 65Å on the emitter cap. This effect, due largely to decreased in-diffusion of arsenic from the mono-emitter, is confirmed by TCAD simulations, as shown in Fig. 4. Similarly, the reduced lateral diffusion of arsenic underneath the L-shaped inside spacers enables re-scaling of the inside spacer width at the bottom of the emitter window to decrease its contribution to the total base resistance. Figure 5 shows the measured minimum noise figure at 30GHz as a function of collector current density for devices with 0.3µm emitter width. It shows the improvement from Gen8 to Gen9 technology, due in this work, to both increased RF performance due to vertical scaling in combination with reductions of the extrinsic base resistance contributions. In conclusion, NXP’s present 0.25µm SiGe BiCMOS processes are suitable for a wide variety of applications and frequency ranges. Process optimization targeted at low noise above 28GHz demonstrates noise performance levels that can easily match processes which feature HBT’s with much higher specified fT/fMAX. References – [1] J.J. Pekarik et al., “A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications”, Proc. BCTM, pp. 92-95, 2014. [2] M. Schröter et al., “SiGe HBT technology: future trends and TCAD-based roadmap”, Proc. IEEE, Vol. 105, No. 6, June 2017. [3] B. Heinemann et al., “SiGe HBT with fT/fmax of 505 GHz/720 GHz”, IEDM 2016, pp. 3.1.1-3.1.4. [4] W.D. van Noort et al., “BiCMOS technology improvements for microwave application”, Proc. BCTM, pp. 93-96, 2008. [5] H. Mertens et al., “Extended High Voltage HBTs in a high-performance BiCMOS process”, Proc. BCTM, pp. 158-161, 2011. [6] J. Melai et al., “QUBiC generation 9, a new BiCMOS process optimized for mmWave applications”, Proc. BCTM, pp. 113-116, 2015. [7] See e.g. chapter 7 in J.D. Cressler and G. Niu, “Silicon-Germanium Heterojunction Bipolar Transistors”, Artech House, ISBN 1-58053-361-2, 2003. Figure 1

Design Optimization of Axial Flux Surface Mounted Permanent Magnet Brushless DC Motor For Electrical Vehicle Based on Genetic Algorithm

This paper presents the design optimization of axial flux surface mounted Permanent Magnet Brushless DC motor based on genetic algorithm for an electrical vehicle application. The rating of the motor calculated form vehicle dynamics is 250 W, 150 rpm. The axial flux surface mounted Permanent Magnet Brushless DC (PMBLDC) motor was designed to fit in the rim of the wheel. There are several design variables e.g. air gap flux density, slot loading, magnet spacer width, ratio of outer to inner diameter, air gap length, current density and space factor). The main contribution in the present work is to propose the best combination of design variables obtained using genetic algorithm (GA) optimization technique and design of motor based on optimized design variables. Final validation is carried out with the help of 3-D finite element analysis (FEA) for GA based constraint and unconstraint design. The entire procedure based on GA is explained with the help of block diagram. Efficiency of the axial flux surface mounted PMBLDC motor is enhanced from 88.15 to 91.5 % using GA based design optimization. Proposed optimization technique and methodology will be useful for performance improvement of any nonlinear engineering design involving various design variables for specific application.

Modeling of a Vertical Hybrid Plasmonic Switch With VO2 Fin Bragg Grating

A 3-D vertical hybrid plasmonic switch having vanadium oxide (VO2) Bragg grating element inside a silicon waveguide has been modeled and simulated in this letter. Narrow bandwidth (30 nm) switching has been achieved maintaining 11.14-dB extinction ratio (ER) at 1.55 $\mu \text{m}$ , effectively due to tailoring VO2 refractive index via heat-induced phase transition. Furthermore, switching response has been assessed by tailoring the number of VO2 fins within the silicon waveguide, oxide spacer dimension, width and height of the silicon waveguide as well, which have impact on the switch behaviour. From numerical simulations, we have found that for 933.4-nm device length with three VO2 fins ~ 11.14-dB ER and 1.57 figure of merit at 1.55- $\mu \text{m}$ wavelength can be obtained.

Enhancement of transition lifetime, linear and nonlinear optical properties in laterally coupled lens-shaped quantum dots for Tera-Hertz range

In this paper, we theoretically study the effects of the structural dimensions, pressure (P) and temperature (T) on transition lifetime (τ), on the linear (α(1)), nonlinear (α(3)) and total α absorption coefficients for Tera-Hertz range (1.2–2.88 THz). The structure under investigation consists of two laterally coupled InAs/GaAs lens-shaped quantum dots (LCQDs) connected to a wetting layer. This structure is analyzed by using the Finite Difference Method (FDM) and the effective mass approximation. The analytical expressions of the transition life time, linear, nonlinear and total absorption coefficients are discussed by using the density matrix formalism. Obtained results show that the total absorption coefficient achieves a maximum value in Tera-Hertz range and the resonant peaks shift toward the lower energies (higher) by increasing the pressure (temperature). Also, the transition lifetime decrease (increase) by increasing the temperature (pressure). As well, the spacer width (between quantum dots) effect is well studied and can be controlled and adjusted. This theoretical study gives a new degree of freedom in describing devices based on laterally coupled QDs and on the intra-band transitions of electrons to achieve desired nonlinear optical properties in Tera-Hertz field.

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.

Asymmetric Drain Extension Dual-kk Trigate Underlap FinFET Based on RF/Analog Circuit.

Among multi-gate field effect transistor (FET) structures, FinFET has better short channel control and ease of manufacturability when compared to other conventional bulk devices. The radio frequency (RF) performance of FinFET is affected by gate-controlled parameters such as transconductance, output conductance, and total gate capacitance. In recent years, high-k spacer dielectric materials for manufacturing nanoscale devices are being widely explored because of their better electrostatic control and being less affected by short channel effects (SCEs). In this paper, we aim to explore the potential benefits of using different Dual-k spacers on source and drain, respectively: (AsymD-kk) trigate FinFET structure to improve the analog/RF figure of merit (FOM) for low-power operation at 14 nm gate length. It has been observed from the results that the AsymD-kk FinFET structure improves the coupling of the gate fringe field to the underlap region towards the source and drain side, improving the transconductance (gm) and output conductance (gds) at the cost of an increase in Miller capacitance. Furthermore, to reduce the drain field influence on the channel region, we also studied the effect of asymmetric drain extension length on a Dual-kk FinFET structure. It can be observed that the new asymmetric drain extension structures significantly improve the cutoff frequency (fT) and maximum oscillation frequency (fmax) given the significant reduction of inner fringe capacitance towards drain side due to the shifting of the drain extension’s doping concentration away from the gate edge. Therefore, the asymmetric drain extension Dual-kk trigate FinFET (AsymD-kkDE) is a new structure that combines different Dual-k spacers on the source and drain and asymmetric drain extension on a single silicon on insulator (SOI) platform to enhance the almost all analog/RF FOM. The proposed structure is verified by technology computer-aided design (TCAD) simulations with varying device physical parameters such as fin height, fin width, aspect ratio, spacer width, spacer material, etc. From comprehensive 3D device simulation, we have demonstrated that the proposed device is superior in performance to a conventional trigate FinFET and can be used to design low-power digital circuits.