Signal Processing Architecture Research Articles

Real-time fast polarization tracking based on polarization phase locking least mean square algorithm.

We propose a fast polarization tracking scheme based on polarization phase locking least mean square (LMS) algorithm and experimentally demonstrate it in real-time implementation with a quasi-feed-forward digital signal processing (DSP) architecture. It has the advantages of no frequency/phase offset feedback requirement from the carrier recovery stage. The tracking performance of the proposed algorithm is verified in both simulation and real-time coherent transmission systems. It can track the state of polarization (SOP) variations up to 12 Mrad/s and 3.3 Mrad/s in 100-Gb/s QPSK and 400-Gb/s 16QAM simulation system, and can track 2.5 Mrad/s in 10-Gb/s QPSK real-time experiment, which has great improvement over conventional LMS algorithm.

The design and implementation of a ROACH2+GPU based correlator on the Tianlai dish array

A digital correlator is a crucial element in a modern radio telescope. In this paper, we describe a scalable design for the correlator system of the Tianlai pathfinder array, which is an experiment dedicated to testing key technologies for conducting a 21 cm intensity mapping survey. The correlator implements the FX design, which firstly performs a fast Fourier transform (FFT) including polyphase filter bank (PFB) computation using a Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) Reconfigurable Open Architecture Computing Hardware-2 (ROACH2) board, then computes cross-correlations by employing Graphics Processing Units (GPUs). The design has been tested both in laboratory and in actual observation.

Delay and Energy Efficient Modular Hybrid Adder for Signal Processor Architectures

In this modern era, high-performance energy efficient devices/systems are the basic requirement for most of the real-time applications. Multiply-accumulate (MAC) units are the frequently used elements in majority of the signal processing architectures. In an MAC unit adders are the basic components. To this end, delay and energy efficient modular hybrid adders for various bit widths are presented. The adder structures are obtained by combining the concatenation and the incrementation schemes to a hybrid structure consisting of modified forms of ripple, carry look ahead, and carry skip adder sections so as to improve delay and energy efficiency. Two versions of hybrid adder architectures are proposed. For n-bit addition, the first adder architecture consists of m numbers of k-bit modified hybrid carry look ahead adder modules, k-bit final sum logic (FSL) stages and output fast carry logic (OFCL) stages. The second adder structure is obtained from the first adder structure by replacing FSL with modified FSL. The speed of addition is improved by the quick and parallel generation of end carry of concatenated adder stages by the modified look ahead carry generation blocks and by the transmission of carries through the modified carry skip action performed by the OFCL blocks. Cadence software with gpdk standard libraries of 45, 90 and 180 nm technology nodes are used for the design and implementation. The values of delay, PDP, and ADP obtained across technology in nm underline the dominance of the proposed adder architectures in terms of delay and energy and area efficiency.

Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing

Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing

Experimental Evaluation of a Control System Based on a Dual-DSP Architecture for a Unified Power Quality Conditioner

An experimental evaluation of a digital control system based on a dual Digital Signal Processor (DSP) architecture is proposed for a three phase Unified Power Quality Conditioner (UPQC). A classical UQPC is constituted by two power conditioners, connected in series and shunted with the power grid, and sharing a common DC-link. In a smart grid scenario of operation, a UPQC will be fundamental for compensating power quality problems, also contributing to improving the efficiency of the electrical grids from a global perspective. The UPQC operation requires a bidirectional energy transfer between the two power conditioners, however, respecting some constraints, they can be controlled independently. In order to take advantage of this characteristic, the control algorithms can be executed on two independent DSPs, without any communication between them and maintaining the operational characteristics of the UPQC. Comparing with the classical control architecture based on a single DSP, with the proposed dual DSP architecture, the computational effort of each DSP is decreased of about 35%, allowing to increase the sampling rate. Therefore, the main advantages of the proposed approach are the minimization of delays caused by the processing time, which are very common in digital control systems, as well as the increment of the UPQC performance. Along the paper, detailed analysis of the processing speed and memory requirements to implement the UPQC control algorithms in both DSPs is presented. The paper also presents a set of detailed experimental results, obtained with a developed 5 kVA laboratory prototype of UPQC, which was used to evaluate the performance of the proposed dual DSP architecture.

An Energy Metering and Measurement SoC With a Novel Low-Power DSP Architecture

This paper presents an energy metering and measurement system-on-a-chip (SoC) with a novel low-power digital signal processor (DSP) architecture. The Cotex-M0-based SoC can measure electricity signals and meter active and reactive energy. It can also monitor the grid by directly accessing and analyzing the waveforms. The measurement and metering algorithms are implemented in a novel DSP architecture with a dedicated reduced instruction set. The filter coefficients and its operating frequency in the default program of DSP can be reprogrammed independently. It can be applied in different applications where demands for metering bandwidth and response time are different. The DSP program can also be reprogrammed by the software if the default program is not desired. The SoC is implemented in a 0.11- ${\mu }\text{m}$ CMOS process. It achieves active and reactive energy metering accuracy of 0.1% with a dynamic range of 5000:1. The analog power supply is 3.3 V and the digital power supply is 1.8 V. The total power consumption of the SoC is ca 17.63 mW with the DSP consuming ca 1.0 mW. Compared with other commercial metering and measurement SoCs, the presented SoC achieves higher metering accuracy and lower power consumption. It is currently in production.

VLSI implementation of residue number system based efficient digital signal processor architecture for wireless sensor nodes

Residue number system (RNS) in computer arithmetic is an efficient parallel computation number system that employs forward conversion, residue arithmetic based arithmetic manipulation and reverses conversion, which all together increases the speed of computation in various digital signal processing applications. Nevertheless power requirement for the wireless sensor node is more important, hence this work focuses on the design and implementation of power efficient RNS based digital signal processor architecture using folded tree based parallel prefix adder by employing Chinese Remainder Theorem—I.

400G Probabilistic Shaped PDM-64QAM Synchronization in the Frequency Domain

A low complexity digital signal processing architecture for dual-polarization coherent detection is presented. It synchronizes impairments in the frequency domain and uses synergies between the filtering processing stages to minimize overall complexity. We show how chromatic dispersion, skew, carrier frequency offset, timing error, and the state of polarization can be mitigated with a single filtering stage in the frequency domain. The error estimation in the frequency domain is based on the modified Godard algorithm, which calculates the clock tone with less than two samples per symbol and small timing jitter. The synchronization in the frequency domain is independent of the modulation format and therefore a good candidate for higher order modulation formats and so the synchronization of probabilistic shaped (PS) signals based on a high cardinality rectangular QAM format. We show the synchronization of PS polarization-division multiplexed (PDM)-64QAM signals with a symbol rate of 42.7 GBd in the frequency domain. The simulative results for the influence of the FFT size and the number of FFT blocks used for the error estimation are shown. Finally, we show experimental results for four different probabilistic shapings in back-to-back and transmission over 300 km, which are synchronized with the introduced digital signal processing (DSP).

Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency

The Multiply-Accumulate Unit (MAC) is an integral computational component of all digital signal processing (DSP) architectures and thus has a significant impact on their speed and power dissipation. Due to an extraordinary explosion in the number of battery-powered “Internet of Things” (IoT) devices, the need for reducing the power consumption of DSP architectures has tremendously increased. Approximate computing (AxC) has been proposed as a potential solution for this problem targeting error-resilient applications. In this paper, we present a novel FPGA implementation for input-aware energy-efficient 8-bit approximate MAC (AxMAC) unit that reduces its power consumption by: performing multiplication operation approximately, or approximating the input operands then replacing multiplication by a simple shift operation. We propose an input-aware conditional block to bypass operands multiplication by (1) zero forwarding for zero-value operands, (2) judiciously approximating 43.8% of inputs into power-of-2 values, and (3) replacing the multiplication of power-of-2 operands by a simple shift operation. Experimental results show that these simplification techniques reduce delay, power and energy consumption with an acceptable quality degradation. We evaluate the effectiveness of the proposed AxMAC units on two image processing applications, i.e., image blending and filtering, and a logistic regression classification application. These applications demonstrate a negligible quality loss, with 66.6% energy reduction and 5% area overhead.

A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems

Millimeter-wave (mm-Wave) communication, operating from 30- to 300-GHz bands with wider available spectrum, has now emerged as a promising solution for future wireless systems. To reduce the hardware complexity of mm-Wave transceivers, beam-selection techniques combined with beamspace multiple-input multiple-output (MIMO) communications have been proposed in the literature. In such a system, beam selection is performed to exploit the near-sparse nature in the mm-Wave channel and, hence, is crucial to the system performance. This paper presents the world’s first digital signal processing (DSP) architecture design for beam selection operation in an mm-Wave multi-user MIMO system. A computationally efficient beam-selection algorithm is first presented. Based on the proposed algorithm, a hardware-scalable beam selection processor is implemented using coordinate rotation digital computers arithmetic. To establish the validity of the concept, the proposed processor is implemented in a 40-nm CMOS technology, integrating 360k logic gates in an area of 0.5625 mm2, while dissipating 44 mW at 266 MHz in an MU-MIMO system with 16 beams and 8 users.

Classification of Epigenetic Biomarkers with Atomically Thin Nanopores.

We use the electronic properties of 2D solid-state nanopore materials to propose a versatile and generally applicable biosensor technology by using a combination of molecular dynamics, nanoscale device simulations, and statistical signal processing algorithms. As a case study, we explore the classification of three epigenetic biomarkers, the methyl-CpG binding domain 1 (MBD-1), MeCP2, and γ-cyclodextrin, attached to double-stranded DNA to identify regions of hyper- or hypomethylations by utilizing a matched filter. We assess the sensing ability of the nanopore device to identify the biomarkers based on their characteristic electronic current signatures. Such a matched filter-based classifier enables real-time identification of the biomarkers that can be easily implemented on chip. This integration of a sensor with signal processing architectures could pave the way toward the development of a multipurpose technology for early disease detection.

Computationally Efficient Bistatic MIMO Radar Signal Processing Architecture Based on Coupling of Range and Direction

Since targets located in the same direction of arrival (DOA) have different directions of departure (DOD), the computation burden of signal processing in bistatic multiple-input multiple-output (MIMO) radar is huge. In this paper, a novel computationally efficient signal processing architecture is proposed for bistatic MIMO radar by exploiting the coupling of range and direction (CRD) property. In the proposed architecture, the echo signals of the targets located in the same DOA are processed first using the same space–time matched filter (STMF) without considering the DOD difference. Due to the CRD, the echo signals can be matched efficiently, but the locations of the targets deviate from their true values in the processing result. Then, through analyzing the CRD thoroughly, an iterative method is proposed to rectify the deviation and the targets’ real location can be obtained accordingly. Since the echo signals of the targets located in the same DOA can be processed effectively with the same STMF, the proposed architecture is more efficient in computation than the conventional one. The convergence property of the proposed iterative method is guaranteed theoretically, and the effectiveness of the new signal processing architecture is verified through numerical experiments.

Performance analysis of dual-frequency receiver using combinations of GPS L1, L5, and L2 civil signals

Processing of GNSS signals from more than one frequency band enhances the accuracy and integrity of a position solution in both standalone and differential positioning. The modern GPS program and newly launched GNSS systems such as GALILEO, BeiDou allow civilians to access signals from multiple frequencies in the L-band spectrum. While there are some advantages in triple-frequency processing in carrier phase applications, in general most of the standalone kinematic receivers get benefit from dual-frequency signals for ionosphere error correction. In implementing a dual-frequency receiver, it is necessary to select a combination of frequencies leading to an optimum performance of the existing civilian signals. In the current research work, we have analyzed the performance of dual-frequency receiver in terms of combined signal observation noise, sensitivity and robustness using analytical models by taking the combination of GPS L1, L2C and L5 signals as an example. Further, we have investigated the benefits of common Doppler estimate-based two-frequency signal tracking to reduce the noise in linear combination of observations. Through analytical and experimental results, it is confirmed that the L1/L5 signal combination in GPS system has low observation noise, which is suitable to use in high accuracy and precise positioning applications using standalone dual-frequency receiver. Further, it is shown that common Doppler estimate-based dual-frequency signal tracking has improved receiver tracking loop performance in terms of observation noise and multipath in linear combination of observations and enhanced receiver sensitivity and robustness. In GPS system, L1/L5 signals processed using common Doppler estimate-aided two-frequency signal tracking architecture, it is possible to effectively mitigate ionosphere delay and other receiver observation errors, to achieve less than 1 m position accuracy using unambiguous code phase observations. Proposed analysis is applicable of finding an optimal two-frequency signal combination in multi-frequency GNSS system and suitable signal processing architecture to obtain high accuracy and precise ionosphere-free position solution using code phase observations in standalone dual-frequency receiver.

Special issue: Design and architectures for real-time signal and image processing

Special issue: Design and architectures for real-time signal and image processing

Maglev Train Signal Processing Architecture Based on Nonlinear Discrete Tracking Differentiator.

In a maglev train levitation system, signal processing plays an important role for the reason that some sensor signals are prone to be corrupted by noise due to the harsh installation and operation environment of sensors and some signals cannot be acquired directly via sensors. Based on these concerns, an architecture based on a new type of nonlinear second-order discrete tracking differentiator is proposed. The function of this signal processing architecture includes filtering signal noise and acquiring needed signals for levitation purposes. The proposed tracking differentiator possesses the advantages of quick convergence, no fluttering, and simple calculation. Tracking differentiator’s frequency characteristics at different parameter values are studied in this paper. The performance of this new type of tracking differentiator is tested in a MATLAB simulation and this tracking-differentiator is implemented in Very-High-Speed Integrated Circuit Hardware Description Language (VHDL). In the end, experiments are conducted separately on a test board and a maglev train model. Simulation and experiment results show that the performance of this novel signal processing architecture can fulfill the real system requirement.

Performance of a wearable acoustic system for fetal movement discrimination.

Fetal movements (FM) are a key factor in clinical management of high-risk pregnancies such as fetal growth restriction. While maternal perception of reduced FM can trigger self-referral to obstetric services, maternal sensation is highly subjective. Objective, reliable monitoring of fetal movement patterns outside clinical environs is not currently possible. A wearable and non-transmitting system capable of sensing fetal movements over extended periods of time would be extremely valuable, not only for monitoring individual fetal health, but also for establishing normal levels of movement in the population at large. Wearable monitors based on accelerometers have previously been proposed as a means of tracking FM, but such systems have difficulty separating maternal and fetal activity and have not matured to the level of clinical use. We introduce a new wearable system based on a novel combination of accelerometers and bespoke acoustic sensors as well as an advanced signal processing architecture to identify and discriminate between types of fetal movements. We validate the system with concurrent ultrasound tests on a cohort of 44 pregnant women and demonstrate that the garment is capable of both detecting and discriminating the vigorous, whole-body ‘startle’ movements of a fetus. These results demonstrate the promise of multimodal sensing for the development of a low-cost, non-transmitting wearable monitor for fetal movements.

Burst-Mode Digital Signal Processing That Pre-Calculates FIR Filter Coefficients for Digital Coherent PON Upstream

This paper proposes a burst-mode digital signal processing architecture for digital coherent time-divisionmultiplexed passive optical network (PON) upstream transmission, wherein two key advances are introduced to shorten the preamble length of burst signals required to complete adaptive equalization, as performed by a constant modulus algorithm: tap coefficients of a finite impulse response (FIR) filter are pre-calculated in the optical network unit (ONU) discovery process, and the feed-forward state of polarization compensation is employed before adaptive equalization. The bit error rate performance attained by the proposal is experimentally evaluated; successful burstmode coherent detection with a high sensitivity of -44.7 dBm is demonstrated for 20 Gbit/s single polarizationquadrature phase shift keying burst signals transmitted over a 40 km single mode fiber, even with the use of a short preamble of 1.3 μs, which meets the optical power specifications required for a 512-way split system. The proposal utilizes register request signals whose preamble is longer than those used in current PON systems to optimize the tap coefficients of the FIR filter, which may disrupt smooth ONU registration in high-splitting-ratio systems. To evaluate this impact, numerical calculations based on the Monte Carlo method are conducted, and the results show that the time required to complete the registration of 512 ONUs is just 40 s or so.

Design of Efficient Mirror Adder in Quantum- Dot Cellular Automata

Lower power consumption is an essential demand for portable multimedia system using digital signal processing algorithms and architectures. Quantum dot cellular automata (QCA) is a rising nano technology for the development of high performance ultra-dense low power digital circuits. QCA based several efficient binary and decimal arithmetic circuits are implemented, however important improvements are still possible. This paper demonstrate Mirror Adder circuit design in QCA. We present comparative study of mirror adder cells designed using conventional CMOS technique and mirror adder cells designed using quantum-dot cellular automata. QCA based mirror adders are better in terms of area by order of three.

High Level Synthesis for Retiming Stochastic VLSI Signal Processing Architectures

With high integration density due to scaling of IC fabrication processes, faster design cycles, are the need of today along with development of energy efficient architectures fulfilling the speed requirements. The focus here is the to build up features of stochastic computing for data centric or data steaming applications. High level synthesis (HLS) allows the designer to incorporate transformations on the applications before the register transfer level (RTL) generation to incorporate design space explorations. Herein the design space explorations start with retiming. Also the novelty is that filter bench marks considered are implemented by incorporating stochastic computing functions. The same are used to develop the filter benchmarks and then retiming transformation is applied in HLS. The design space trade off results with respect to retiming transformations on conventional computation and stochastic computing architectures are presented, for area and power and it is found that stochastic computing results in area saving and power saving scales relatively for higher order applications namely the filter benchmarks showing that stochastic structures to be energy efficient than conventional computing. The future scope of the work is to consider accuracy analysis based on end user demand of accuracy versus energy efficiency.

Efficient FPGA-based FIR – architecture and its significance in ultrasonic signal processing

The presented work demonstrates the most suitable architecture for the FPGA-based signal processing which makes available various real-time filtering algorithms, such as band pass, high pass, low pass, and band-reject for FIR filters. The processor was implemented with the fixed-point arithmetic using VHDL, which can be downloadable on FPGA device. The FPGA device can be interfaced with an analog-to-digital converter (ADC), digital-to-analog converter (DAC) and a personal computer with MATLAB for the user interface and feeding coefficients and order of the filter. The core part of this paper was to find the reconfigurable and efficient architecture of the processor with only one multiplier which can work for Finite Impulse response (FIR) filter with the best- suited structure. The system will be used for automatic generation of fixed-point FIR filters. The model was also implemented in MATLAB script and the verification of results in the case of low-pass filtering confirmed that both models in MATLAB and VHDL matched to each other. All components of architecture in VHDL were designed using generics which allow changing its structure and behavior by generic values. Therefore, it is a universal filter platform where user can process the data while changing the filter parameters as per the requirement of applications. The complete design was verified by taking the example of audio signal frequency, but parameterized components of system architecture can also facilitate its applicability at ultrasonic frequencies by changing the algorithm. The significance and applicability of FPGAs in ultrasonic signal processing were also studied and reviewed.