Abstract

The Multiply-Accumulate Unit (MAC) is an integral computational component of all digital signal processing (DSP) architectures and thus has a significant impact on their speed and power dissipation. Due to an extraordinary explosion in the number of battery-powered “Internet of Things” (IoT) devices, the need for reducing the power consumption of DSP architectures has tremendously increased. Approximate computing (AxC) has been proposed as a potential solution for this problem targeting error-resilient applications. In this paper, we present a novel FPGA implementation for input-aware energy-efficient 8-bit approximate MAC (AxMAC) unit that reduces its power consumption by: performing multiplication operation approximately, or approximating the input operands then replacing multiplication by a simple shift operation. We propose an input-aware conditional block to bypass operands multiplication by (1) zero forwarding for zero-value operands, (2) judiciously approximating 43.8% of inputs into power-of-2 values, and (3) replacing the multiplication of power-of-2 operands by a simple shift operation. Experimental results show that these simplification techniques reduce delay, power and energy consumption with an acceptable quality degradation. We evaluate the effectiveness of the proposed AxMAC units on two image processing applications, i.e., image blending and filtering, and a logistic regression classification application. These applications demonstrate a negligible quality loss, with 66.6% energy reduction and 5% area overhead.

Highlights

  • The nascent approximate computing (AxC) design paradigm is a promising approach for designing power- and areaefficient digital circuits, which are quite suitable for batterypowered devices

  • (2) 20-bit Binary Adder: Targeting a low-power highspeed MAC design, we design and evaluate various 20-bit binary adders, i.e., ripple carry adder (RCA), carry look ahead adder (CLA) and carry select adder (CSA), we evaluate the performance analysis for each adder, including its area, delay and power consumption based on its register transfer level (RTL) implementation

  • We evaluate our MAC units against a logistic regression classifier to predict whether a student gets admitted into a university [41]

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Summary

INTRODUCTION

The nascent approximate computing (AxC) design paradigm is a promising approach for designing power- and areaefficient digital circuits, which are quite suitable for batterypowered devices. The CEVA-NP4000 DSP processor includes 4096 8×8 MAC units [5], which are used in various high-performance energy-constrained edge processing applications, i.e., IoT, smart-phones and enterprise surveillance. We believe that these requirements can be attained by designing energy-efficient approximate MAC (AxMAC) units that are suitable for error-resilient applications. We target the multiplier and controller blocks as we propose an energy-efficient input-aware unsigned 8-bit approximate MAC unit. We propose an FPGA implementation for five designs of an energy-efficient unsigned 8-bit approximate MAC (AxMAC) units.

CONVENTIONAL MAC UNIT
PRELIMINARIES
18: Check for special-cases of Xi and Yi
APPLICATIONS
Findings
CONCLUSION
Full Text
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