Comparative Analysis of different Algorithm for Design of High-Speed Multiplier Accumulator Unit (MAC)

Abstract

Background/Objectives: Power consumption is one of the important designsin many digital signal processing applications, the main building blocks of the processor is Multiplier-Accumulator (MAC) unit. Methods/Statistical Analysis: In the present work, the Baugh-Wooley multiplier is implemented for improving the performance of MAC unit. The Baugh wooley multiplier is faster than the other multipliers like Array multiplier, Wallace tree multiplier, Booth multiplier. The MAC unit using Baugh-Wooley multiplier is implemented using 180nm technology in cadence virtuoso. Findings: The speed of MAC unit using Wallace tree multiplier is 93.6MHz and with Baugh wooley multiplier is 99.1MHz. The power consumption of the MAC unit using Wallace tree multiplier is 2.265mW and with Baugh wooley multiplier is 4.628mW. The results show that the MAC unit using Baugh wooley multiplier is faster than the Wallace tree multiplier. Application/Improvements: MAC unit processors. In future, we can implement MAC unit using Baugh wooley multiplier with apipelining technique such that the total power consumption will be less.