Abstract
In recent years, for various highperformance applications Multiply-Accumulate (MAC) unit is being developed. MAC is vital element in digital signal processing system (DSP). It is used for coefficient multiplication, filtering etc. In the existing MAC unit model, multiplier is designed using Radix-2 booth multiplier. In this work, a different arithmetic based multiply-accumulate (MAC) unit is designed. Here, modified Radix-4 booth multiplier scheme is used to improve the delay performance of MAC unit. For the partial product reduction and accumulate operations, the (6,3) counters are used. This results in high performance in the system. Designed MAC units have 16×16-bit multiplier with 40-digit accumulate output. It is synthesized and simulated using ISE Xilinx 14.5 and implemented on Spartan 6 FPGA (XC6LX9-2TQGI44). It provides better performance compared to conventional pipelined carry propagate multiply-accumulate units.
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